SRAM Memory Reset Circuit with Precharged Bit Lines
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Solution Overview
Problem
Conventional SRAM memory technologies face challenges in performing fast and low-power consumption resets, particularly in applications like time-of-flight ranging and LiDAR, where frequent resets of large blocks of memory cells are required, leading to inefficiencies in clock cycles and power consumption.
Innovation Solution
A method involving precharging bit lines, asserting a reset signal to release the precharge voltage, selecting write drivers to change bit line logic states, and asserting word lines to write desired logic states to all memory cells within a single clock cycle, without reapplying precharge voltage between resets, allowing for simultaneous or sequential resetting of multiple rows with reduced power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional write operations are performed for each word to reset memory cells, then data integrity is maintained, but the number of clock cycles increases linearly with the number of words to be reset
Solution Approach 1:
The memory array is segmented into multiple banks, allowing parallel reset operations to be performed simultaneously on different banks. This reduces the overall reset time from O(N) sequential operations to O(N/k) parallel operations where k is the number of banks
Solution Approach 2:
Bit lines are precharged to a specific voltage level before the reset operation begins. This preliminary action enables the write drivers to immediately drive the bit lines to the desired logic state when activated, eliminating the need for gradual charging/discharging during the reset operation and reducing the clock cycles required
2Ease of operation
If precharge voltage is reapplied to bit lines between each write operation during reset, then bit lines are ready for subsequent operations, but power consumption increases significantly
Solution Approach 1:
The bit lines maintain their precharged state continuously throughout the reset operation rather than being recharged between each write operation. Multiple write operations are performed on the same bit lines without interrupting the precharge, eliminating redundant charging cycles and reducing power consumption proportionally to the number of operations performed on the same bit lines
Solution Approach 2:
The precharge operation is performed periodically at the beginning of each bank reset operation rather than continuously between every write operation. This periodic approach maintains bit line readiness while significantly reducing the frequency of high-power precharge events
Data Source
AI summary
A method of memory reset includes precharging bit lines of a memory array, asserting a signal at a reset node to remove the precharge voltage, and selecting write drivers associated with the bit lines associated with columns of the memory array that contain memory cells to be reset, with the assertion of the signal at the reset node also resulting in application of desired logic states to inputs of the selected write drivers to cause those selected write drivers to change a logic state of the bit lines associated with those write drivers. The method continues with asserting each word line associated with a row of the memory that contains memory cells to be reset to write desired logic states to all of the memory cells of the columns and rows of the memory to be reset during a single clock cycle, and then deasserting those word lines.