SRAM Array Reset via Metastable State Injection
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Solution Overview
Problem
Existing SRAM designs face challenges in performing fast resets and content corruptions across multiple memory cells within a single clock cycle, while also minimizing power consumption and current sinking requirements.
Innovation Solution
The proposed solution involves a method that includes asserting a signal at a reset node to starve the current supply, selecting bit lines and complementary bit lines for desired columns, forcing these lines to a same logic state, and simultaneously asserting and deasserting word lines to place memory cells into a metastable state within a single clock cycle. This is achieved through a virtual power supply circuit that reduces current output, allowing for reduced power consumption and increased efficiency in resetting or corrupting memory cell contents.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If conventional write operations are performed to reset memory cells, then memory cells can be reset to desired logic values, but the process requires multiple clock cycles and consumes excessive power
Solution Approach 1:
The patent changes the operating parameters of the memory cells by forcing bit lines and complementary bit lines to the same logic state, which is outside the normal read/write operating conditions. This parameter change enables the cells to be driven into a metastable state that can be resolved to either logic 0 or logic 1, achieving reset in a single clock cycle with reduced power consumption compared to conventional sequential write operations
Solution Approach 2:
The patent employs periodic clocked control signals to systematically drive the memory cells through the reset process. By using clocked control to periodically assert and deassert word lines in coordination with bit line forcing, the system achieves synchronized reset of multiple memory cells within a single clock cycle, improving productivity while maintaining controlled power consumption
2Productivity
If multiple memory cells are reset simultaneously, then reset speed increases, but current sinking requirements increase
Solution Approach 1:
The patent changes the voltage parameters of the bit lines by forcing them to extreme logic states (both high or both low) rather than using normal write differential signals. This parameter change allows simultaneous control of multiple memory cells while limiting the current sinking requirement to only what is needed to maintain the forced state, not to drive transitions in each cell individually
Solution Approach 2:
The patent segments the memory array into multiple independently controllable blocks, each with its own set of bit lines and word lines. This segmentation allows different blocks to be reset simultaneously without requiring the entire array to be driven by a single high-current write driver, thereby achieving high productivity while distributing and limiting current sinking requirements across multiple smaller segments
Data Source
AI summary
A method of corrupting contents of a memory array includes asserting a signal at a reset node to thereby cause starving of current supply to the memory array, and selecting bit lines and complementary bit lines associated with desired columns of the memory array that contain memory cells to have their contents corrupted. For each desired column, a logic state of its bit line and complementary bit line are forced to a same logic state. Each word line associated with desired rows of the memory array that contains memory cells to have their contents corrupted is simultaneously asserted, and then simultaneously deasserted to thereby place each memory cell to have its contents corrupted into a metastable state during a single clock cycle.