SRAM Retention Voltage Generation Circuit for Low Power Wearables
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Solution Overview
Problem
Current SRAM designs for wearable devices face challenges in reducing power consumption and chip area while maintaining data stability, as existing double-source voltage structures increase dynamic power consumption and require external circuits, affecting noise margin and storage stability.
Innovation Solution
A retention voltage generation circuit that includes a driving circuit, a first retention voltage generation circuit for NMOS transistors, a second for PMOS transistors, and a selection circuit to autonomously select the higher voltage as a retention voltage, allowing the power-consumption circuit to operate in a retention mode without external auxiliary circuits.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of energy
If a double-source voltage structure is used to reduce SRAM supply voltage for low power consumption, then power consumption is reduced, but noise margin is reduced and data stability is affected
Solution Approach 1:
The patent dynamically adjusts the retention voltage parameter based on operational mode (retention mode vs. normal mode). In retention mode, the supply voltage is reduced to DRV (data retention voltage) to minimize power consumption while maintaining data stability. The voltage level is precisely controlled through a retention voltage generation circuit that ensures the voltage remains within the stable retention range, thus resolving the contradiction between power reduction and data stability.
2Loss of energy
If a double-source voltage structure is used to generate retention voltage, then power consumption is reduced, but circuit area increases due to external circuits
Solution Approach 1:
The patent merges the retention voltage generation function with the existing power consumption circuit by integrating a retention voltage generation circuit within the SRAM structure. This eliminates the need for external voltage switching circuits, thereby reducing the overall IC chip area while maintaining the low power consumption benefit of retention mode operation.
Solution Approach 2:
The retention voltage generation circuit is designed to autonomously generate and regulate the retention voltage without requiring external control circuits. The circuit self-regulates the voltage level based on internal reference voltages and switching mechanisms, making the system self-sufficient and eliminating external auxiliary circuits that would increase chip area.
3Loss of energy
If source voltage is switched between two statuses using a double-source voltage structure, then retention mode is achieved, but extra time and dynamic power consumption are required
Solution Approach 1:
The retention voltage generation circuit is pre-configured with reference voltages and switching pathways that are ready before voltage transitions are needed. The circuit maintains pre-charged capacitors and pre-positioned switching elements that enable rapid voltage transitions without requiring extensive charging/discharging time, thus minimizing the time loss during mode switching.
Solution Approach 2:
The patent implements a dynamic voltage switching mechanism that can rapidly transition between retention voltage and normal operating voltage. The switching circuit uses controlled switches and buffered stages that enable fast voltage changes, reducing the transition time and associated dynamic power consumption while achieving the low-power retention mode.
Data Source
AI summary
Retention voltage generation circuits and electronic apparatus are provided. An exemplary retention voltage generation circuit includes a driving circuit, configured to generate driving currents; a first retention voltage generation circuit, configured to generate a first retention voltage, the first retention voltage being substantially equal to a threshold voltage of an NMOS transistor in a power-consumption circuit; a second retention voltage generation circuit, configured to generate a second retention voltage, the second retention voltage being substantially equal to a threshold voltage of a PMOS transistor in the power-consumption circuit; and a retention voltage selection circuit, coupled to the first retention voltage generation circuit and the second retention voltage generation circuit, and configured to receive the driving currents, wherein retention voltage selection circuit is configured to select a higher voltage from the first retention voltage and the second retention voltage as a retention voltage to drive the power-consumption circuit to operate at a retention mode.