Programmable SRAM Cell Supply Voltage for Low-Leakage Retention
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
SRAM structures experience significant leakage current during retention mode due to the large difference between the positive and ground cell supply voltages, which affects data retention efficiency.
Innovation Solution
A memory structure with a programmable low cell supply voltage (Vcsl) and a programming circuit that includes transistors with different threshold voltages, allowing Vcsl to be set to ground in operational mode for robust operations and to a selectable voltage in retention mode to reduce leakage current.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a large difference between Vcs and Vss is used to facilitate robust read and write operations, then operational reliability is improved, but leakage current during retention mode increases significantly
Solution Approach 1:
The patent applies dynamics by making the cell supply voltage Vcs dynamically adjustable rather than fixed. A programming circuit with multiple transistors having different threshold voltages allows Vcs to be selectively programmed to different voltage levels. During operational mode, Vcs is set to a higher level for robust read/write operations, while during retention mode, Vcs is reduced to minimize leakage current, thus resolving the contradiction between operational reliability and energy loss.
Solution Approach 2:
The patent employs parameter changes by varying the cell supply voltage Vcs based on operational mode. The programming circuit enables Vcs to be programmed to different voltage levels: a higher voltage difference (Vcs-Vss) during operational mode for reliable read/write operations, and a lower voltage difference during retention mode to reduce leakage current. This dynamic parameter adjustment resolves the technical contradiction between maintaining operational reliability and minimizing energy loss.
2Loss of energy
If Vcs is set to ground in retention mode to reduce leakage current, then energy loss is reduced, but data retention capability deteriorates
Solution Approach 1:
The patent applies parameter changes by programming Vcs to an intermediate voltage level during retention mode rather than setting it to ground. The programming circuit with transistors of different threshold voltages enables selective setting of Vcs to a voltage that is sufficiently high to maintain data retention capability while being low enough to significantly reduce leakage current compared to operational mode, thus resolving the contradiction between energy loss and data retention capability.
3Adaptability or versatility
If multiple transistors with different threshold voltages are used in the programming circuit, then adaptability is improved, but device complexity increases
Solution Approach 1:
The patent applies segmentation by dividing the programming circuit into multiple discrete transistor elements, each with a specific threshold voltage characteristic. These segmented transistor components can be selectively activated through control signals to program Vcs to different voltage levels. This segmentation provides adaptability for various voltage programming needs while keeping each individual transistor component simple, thus managing the trade-off between adaptability and device complexity.
Data Source
AI summary
A disclosed memory structure includes memory cells connected to first and second cell supply voltage lines. A programming circuit enables programming of a low cell supply voltage (Vcsl) on the first cell supply voltage line and includes transistors with different threshold voltages connected to ground and further connectable, via switches, to the first cell supply voltage line. The programming circuit can further include an additional switch connected between ground and the first cell supply voltage line. In an operational mode, the first cell supply voltage line is discharged to ground via the additional switch. In the retention mode, one of the transistors of the programming circuit is connected by a corresponding switch to the first cell supply voltage line for programming of Vcsl. Optionally, the memory structure can be implemented in FDSOI and the transistors of the programming circuit can also be back biased for fine tuning of Vcsl.