SRAM Ring Oscillator via Interconnect Layers for Speed Measurement
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Solution Overview
Problem
Existing integrated circuits face challenges in estimating the speed of Static Random Access Memory (SRAM) cells without altering their internal structure or adding costly interconnections, as advanced process nodes require adherence to strict design rules.
Innovation Solution
A ring oscillator is constructed using standard-library SRAM cells with interconnections made in separate layers, allowing access only through cell-interfaces, and control logic is used to trigger oscillations whose frequency indicates the speed of the SRAM cells, without modifying the internal logic or structure of the SRAM cells.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If SRAM cell internal structure is modified to enable speed estimation, then measurement capability is improved, but manufacturing complexity and cost increase
Solution Approach 1:
The patent divides the SRAM cell into functional segments: the standard cell interface remains unchanged while separate interconnection layers are added to form the ring oscillator. This segmentation allows speed measurement functionality to be added without modifying the core SRAM cell structure, resolving the contradiction between measurement capability and manufacturing complexity.
Solution Approach 2:
The patent introduces an intermediary layer of interconnections that mediates between the standard SRAM cell interfaces and the ring oscillator functionality. These interconnections act as a bridge, enabling speed estimation without direct modification of the SRAM cell internal structure, thus maintaining manufacturing simplicity while achieving measurement capability.
2Manufacturing precision
If standard design rules are strictly followed for advanced process nodes, then manufacturing precision is maintained, but speed estimation capability is limited
Solution Approach 1:
The patent transitions from a two-dimensional planar interconnection approach to a three-dimensional layered interconnection structure. By utilizing vertical stacking of interconnection layers above the standard SRAM cell layout, the patent enables ring oscillator formation without violating planar design rules, thus maintaining manufacturing precision while achieving speed estimation capability.
3Measurement precision
If SRAM cells are interconnected to form ring oscillator, then speed measurement is enabled, but interconnection cost and complexity increase
Solution Approach 1:
The patent designs the interconnection layers to serve multiple functions: they form the ring oscillator for speed measurement while also maintaining compatibility with standard SRAM cell operation. The same interconnection infrastructure supports both memory functionality and oscillator functionality, reducing overall complexity and cost compared to dedicated measurement structures.
Data Source
AI summary
An Integrated Circuit (IC) includes a memory, circuit interconnections and control logic. The memory includes multiple standard-library Static Random Access Memory (SRAM) cells disposed on a substrate of the IC in multiple first layers, so that access to a respective SRAM cell to read and write data is through a cell-interface. The circuit interconnections, fabricated in one or more second layers separate from the first layers, interconnect cell-interfaces of a subgroup of the SRAM cells to form a ring oscillator that includes a cascade of N stages defined by the interconnected SRAM cells. The control logic is coupled to the cell-interfaces via the circuit interconnections, and is configured to apply an input signal to one or more of the cell-interfaces so as to trigger an oscillation of the ring oscillator whose frequency of oscillation is indicative of a speed of the SRAM cells of the memory.