Pseudo-Triple-Port SRAM Scan Mode for Parallel DFT Testing
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Solution Overview
Problem
Conventional triple-port SRAMs incur a density penalty due to additional access transistors per bitcell, and existing scan modes complicate the testing of peripheral logic components.
Innovation Solution
A pseudo-triple-port SRAM design with a scan mode that synchronizes read and write operations using a 'double pumped' memory clock signal, bypassing multiplexers during scan mode, and includes a bypass scan logic circuit to level-shift scan signals, allowing full scanning of peripheral logic components without interfering with normal operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If DFT testing is implemented on traditional memory macro architecture, then manufacturing defects can be detected, but test access time increases and testing cannot occur in parallel across all memory banks
Solution Approach 1:
The memory array is divided into multiple independently testable memory banks (first memory bank, second memory bank, etc.), each with its own set of scan chains. This segmentation allows parallel testing of different banks, reducing total test time while maintaining comprehensive defect detection coverage across the entire memory macro.
Solution Approach 2:
The patent introduces a new dimension of parallelism by organizing scan chains across multiple memory banks simultaneously, rather than sequentially accessing single banks. Multiple scan chains can operate in parallel within and across banks, transforming the testing process from a sequential single-dimension operation to a parallel multi-dimensional operation.
2Ease of manufacture
If traditional memory macro architecture is used, then standard memory operations are supported, but DFT testing requires sequential access and cannot test multiple banks in parallel
Solution Approach 1:
The memory macro architecture is designed with dual functionality: it supports both standard memory operations and DFT testing operations through the same physical structure. The scan chains can operate in testing mode while the memory banks maintain their normal operational mode, allowing the system to serve multiple purposes without requiring separate dedicated test hardware for each bank.
Solution Approach 2:
The architecture dynamically switches between operational modes (standard memory operation vs. DFT testing) and enables dynamic parallelism where different memory banks can be tested simultaneously. The scan chain configuration allows flexible allocation of test resources across banks based on testing requirements, optimizing productivity without sacrificing ease of manufacture.
3Reliability
If scan chains are added for DFT testing, then defect detection is enabled, but the memory macro architecture becomes more complex
Solution Approach 1:
The scan chains are merged with the existing memory bank structure, sharing physical resources such as word lines, bit lines, and sense amplifiers. Rather than adding completely separate test infrastructure, the scan chains are integrated into the memory macro architecture, combining testing functionality with the existing memory structure to minimize additional complexity while enabling comprehensive defect detection.
Data Source
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AI summary
A memory is provided with a clock circuit configured to simultaneously assert a write multiplexer clock signal and a read multiplexer clock signal during a scan mode of operation. In the scan mode of operation, a scan in signal routes through a write multiplexer to a first bit line while the write multiplexer clock signal is asserted. Similarly, the scan in signal routes from the first bit line through a read multiplexer while the read multiplexer clock signal is asserted.