8-Transistor SRAM Cell with Schottky Diodes for Column Select
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Solution Overview
Problem
8-transistor SRAM cell designs face challenges in achieving column select functionality without causing write disturbs, as existing designs are optimized for writing and cannot simultaneously ensure read stability and writeability, leading to unintended writing of bits in other columns.
Innovation Solution
Incorporating Schottky diodes in the 8-transistor SRAM cell design, specifically placing them in series between pull-up and pull-down transistors to block charge transfer during write operations, and altering pass gates for asymmetric behavior, allowing column select writing without disturbing adjacent bits.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If strong pass gates are used to improve writeability, then write margin is improved, but column select functionality deteriorates causing unintended writing of bits in other columns
Solution Approach 1:
Schottky diodes are introduced as intermediary elements between the pass gates and the storage nodes. These diodes act as controlled conduits that permit charge transfer during intended write operations while blocking charge transfer during column select operations, thereby enabling column select functionality without compromising write margin
Solution Approach 2:
The electrical characteristics of the pass gates are dynamically controlled by changing the voltage state of the word line. When the word line is at write voltage, full write capability is enabled. When the word line is at read voltage, the pass gate behavior changes to enable column select functionality, thus adapting the same hardware to multiple operational modes
2Reliability
If pass gates are optimized for write operations, then writeability is improved, but read stability deteriorates due to inability to simultaneously optimize both conditions
Solution Approach 1:
The pass gates are designed to be dynamically controllable through word line voltage switching. The same pass gates exhibit different effective strengths depending on the word line voltage state, allowing the system to optimize for write operations during write mode and maintain read stability during read mode without requiring separate dedicated structures
Solution Approach 2:
Schottky diodes serve as mediators that decouple the direct coupling between pass gates and storage nodes during read operations. This intermediary structure allows read transistors to affect the signal on read bit lines while preventing full charge transfer that would compromise read stability
3Stability of the object's composition
If 8-transistor cell structure is used to decouple read and write operations, then read stability is improved, but column select functionality deteriorates due to strong pass gates causing unintended writes
Solution Approach 1:
Schottky diodes are strategically placed in the 8-transistor cell structure to mediate between the strong pass gates and the storage nodes. This intermediary structure allows the benefits of strong pass gates (improved writeability and read stability) to coexist with column select functionality by controlling charge transfer paths based on operational mode
Solution Approach 2:
The Schottky diodes create localized control over charge transfer paths within the 8-transistor cell. By placing diodes at specific locations in the circuit, the invention enables differential behavior in different parts of the cell during column select operations, allowing intended writes while blocking unintended writes to adjacent columns
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
Enables column select writing functionality while maintaining write margin advantages and preventing cell disturbs, ensuring the bit value remains unchanged during read operations.
Implementation Method 1
Incorporating Schottky diodes in the 8-transistor SRAM cell design, specifically placing them in series between pull-up and pull-down transistors to block charge transfer during write operations
Data Source
AI summary
An 8-transistor SRAM cell which includes two pull-up transistors and two pull-down transistors in cross-coupled inverter configuration to form two inverters for storing a single data bit, wherein each of the inverters includes a Schottky diode; first and second pass gate transistors having a gate terminal coupled to a write word line and a source or drain of each of the pass gate transistors coupled to a write bit line; and first and second read transistors coupled to the two pull-up and two pull-down transistors, one of the read transistors having a gate terminal coupled to a read word line and a source or a drain coupled to a read bit line. In a preferred embodiment, the 8-transistor SRAM cell has column select writing enabled for writing a value to the 8-transistor SRAM cell without inadvertently also writing a value to another 8-transistor SRAM cell.