6T-SRAM Cell Design Using Segmented Fin Structures
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
The challenge in manufacturing static random-access memory (SRAM) cell designs is the increased complexity and variability in cell layout as transistors shrink in size, particularly in achieving optimal performance and scalability with fin field effect transistors (finFETs) for advanced technology nodes.
Innovation Solution
The development of a 6T-SRAM cell design using a single fin for both n-type and p-type doped field effect transistors, with a silicon germanium layer epitaxially grown on a silicon substrate, allowing for adjustable active fin height to optimize channel width ratios and reduce area consumption while maintaining high performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If transistor size is reduced to increase performance and reduce power consumption, then device density and efficiency are improved, but manufacturing complexity and layout variability increase
Solution Approach 1:
The patent segments the fin structure into distinct regions with different crystal orientations by creating trenches at specific locations. This segmentation allows different fins to have different orientations (e.g., <100> vs <110>), enabling independent optimization of nFET and pFET characteristics while maintaining a unified cell layout, thus reducing manufacturing complexity despite continued scaling.
Solution Approach 2:
The patent applies local quality by introducing trenches selectively at specific locations within the fin structure to create regions with different crystal orientations. This localized modification allows precise control over transistor characteristics in specific areas without affecting the entire structure, enabling optimized performance while maintaining scalability.
2Reliability
If fin height is increased to improve transistor performance, then channel control is enhanced, but area consumption increases
Solution Approach 1:
The patent introduces asymmetry by creating trenches at specific locations that cause fins to have different heights or orientations in different regions. This asymmetric structure allows the channel to be longer or have better control in critical areas without uniformly increasing the area of the entire fin structure, thus improving performance without proportional area penalty.
Solution Approach 2:
The patent moves the solution from a two-dimensional planar layout to a three-dimensional structured fin with trenches. By introducing vertical dimensionality through trenches that extend into the substrate, the patent achieves better channel control and performance without increasing the horizontal footprint of the cell.
3Reliability
If different fin orientations are used to optimize nFET and pFET characteristics, then device performance is improved, but manufacturing precision requirements increase
Solution Approach 1:
The patent applies preliminary action by pre-defining trench locations and orientations during the fabrication process before final transistor formation. The trenches are created at specific crystallographic orientations using predetermined patterning steps, which guides subsequent processing and ensures consistent fin orientations without requiring high-precision alignment at each subsequent step.
Solution Approach 2:
The patent uses trenches as an intermediary structure that mediates between the substrate crystal orientation and the final fin structure. The trenches act as templates or guides that automatically define fin orientations based on their own geometry and position, reducing the need for complex alignment procedures and high manufacturing precision requirements.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables flexible SRAM design without area penalty, providing high performance and density by adjusting the effective channel width ratios for different applications, thus addressing the limitations of prior designs that relied on stronger nFETs and more fins for pFETs.
Implementation Method 1
A silicon germanium layer is epitaxially grown onto the exposed portions of the silicon substrate and in the trench feature
Data Source
AI summary
6T-SRAM cell designs for larger SRAM arrays and methods of manufacture generally include a single fin device for both nFET (pass-gate (PG) and pull-down (PD)) and pFET (pull-up (PU). The pFET can be configured with a smaller effective channel width (Weff) than the nFET or with a smaller active fin height. An SRAM big cell consumes the (111) 6t-SRAM design area while provide different Weff ratios other than 1:1 for PU/PD or PU/PG as can be desired for different SRAM designs.