SRAM Transistor Strain Engineering via Selective Epitaxial Growth
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Solution Overview
Problem
Advanced SRAM devices face defects and degraded electrical characteristics due to selective epitaxial growth in moat tip regions, leading to high off-state current and subsurface leakage, which hinder carrier mobility and transistor performance.
Innovation Solution
The method involves masking moat tip regions during epitaxial growth to prevent thinning and defects, using silicon germanium deposition only in specific source and drain regions to apply strain effectively, thereby reducing threading dislocation defects and enhancing carrier mobility without compromising drive current.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If selective epitaxial growth is performed in moat tip regions to provide strain in source and drain regions, then carrier mobility is enhanced, but threading dislocation defects occur due to reduced dimensions preventing proper epitaxial growth
Solution Approach 1:
The patent applies different treatments to different regions: selective epitaxial growth is performed only in source and drain regions away from moat tips, while moat tip regions are protected from etching and growth. This local differentiation allows strain to be applied where beneficial without causing defects in constrained geometries.
Solution Approach 2:
The source and drain regions are segmented into two zones: regions suitable for selective epitaxial growth (away from moat tips) and moat tip regions that are protected. This segmentation allows the patent to apply strain enhancement selectively while avoiding defect-prone areas.
2Reliability
If selective epitaxial growth is performed in moat tip regions, then strain is introduced to enhance carrier mobility, but contact and silicide formation are degraded
Solution Approach 1:
The patent introduces strain locally in source and drain regions through selective epitaxial growth while protecting moat tip regions. This prevents the formation of defects that would otherwise degrade contact and silicide formation quality in these constrained regions.
3Reliability
If selective epitaxial growth is performed in moat tip regions, then strain is applied to improve carrier mobility, but off-state current increases due to subsurface leakage
Solution Approach 1:
The patent applies strain enhancement locally in source and drain regions while protecting moat tip regions from selective epitaxial growth. This prevents the creation of subsurface leakage paths that would increase off-state current, thereby maintaining low power consumption while still achieving carrier mobility enhancement.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach improves carrier mobility and drive current in SRAM transistors while minimizing defects associated with selective epitaxial growth in moat tip regions, reducing leakage and enhancing transistor performance.
Implementation Method 1
The most common method of introducing strain in a silicon channel region is to recess the source and drain regions adjacent to the channel and to fill the recessed regions with a stressor material by selective epitaxial growth
Implementation Method 2
A compressive strained channel has significant hole mobility enhancement over conventional devices. A tensile strained channel achieves significant electron mobility enhancement
Data Source
AI summary
An SRAM device and method of forming MOS transistors of the device having reduced defects associated with selective epitaxial growth in moat tip regions is discussed. The SRAM device comprises a core region and a logic region, logic transistors within the logic region of the SRAM, and selective epitaxial regions grown on both source and drain regions; and memory cell transistors within the core region of the SRAM, and having the selective epitaxial regions grown on only one of the source and drain regions. One method of forming the MOS transistors of the SRAM cell comprises forming a gate structure over a first conductivity type substrate to define a channel therein, masking one of the source and drain regions in the core region, forming a recess in the substrate of the unmasked side of the channel, epitaxially growing SiGe in the recess, removing the mask, and forming the source and drain extension regions in source/drain regions.