SRAM Memory Control with Selective Data Retention

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Solution Overview

Problem

SRAM memory circuits face a dilemma where either low leakage or fast operating speed can be achieved, but not both, and existing solutions fail to provide flexible data retention for selected groups of memory cells, leading to inefficient power management and potential data loss during standby mode.

Innovation Solution

A memory circuit with fine-grained control over retention and non-retention modes is implemented using local data retention information, allowing adaptive selection of SRAM cell groups and programming retention information during write access, utilizing switching means to manage virtual supply lines and minimize leakage current.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Speed

If low-threshold transistors are used, then fast operating speed is achieved, but leakage current increases

Engineering Contradiction:
Improveoperating speedVSAvoidleakage current
Core Design Contradiction:
SpeedVSLoss of energy

Solution Approach 1:

The SRAM array is divided into multiple groups, each with independent control logic that can selectively enable or disable retention mode. This segmentation allows different regions to operate with different threshold voltage characteristics based on their specific functional requirements, resolving the contradiction between speed and leakage current.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent implements dynamic control of retention mode through control logic that can switch between retention and non-retention states based on operational requirements. This dynamic adjustment allows the system to optimize between leakage current and operating speed depending on the current operational context.

Inventive Principle:
Principle #15Dynamics

2Loss of energy

If high-threshold transistors are used, then leakage current is reduced, but operating speed decreases

Engineering Contradiction:
Improveleakage currentVSAvoidoperating speed
Core Design Contradiction:
Loss of energyVSSpeed

Solution Approach 1:

The SRAM array is divided into multiple groups, each with independent control logic that can selectively enable or disable retention mode. This segmentation allows different regions to operate with different threshold voltage characteristics based on their specific functional requirements, resolving the contradiction between speed and leakage current.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent implements dynamic control of retention mode through control logic that can switch between retention and non-retention states based on operational requirements. This dynamic adjustment allows the system to optimize between leakage current and operating speed depending on the current operational context.

Inventive Principle:
Principle #15Dynamics

3Reliability

If all SRAM cells retain data during standby, then data retention is ensured, but power consumption increases

Engineering Contradiction:
Improvedata retentionVSAvoidpower consumption
Core Design Contradiction:
ReliabilityVSUse of energy by stationary object

Solution Approach 1:

The SRAM array is divided into multiple groups with independent retention control. This allows the system to retain data only in those groups that require it, while allowing other groups to enter a lower-power state, thereby reducing overall power consumption while maintaining necessary data retention.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

Different groups of SRAM cells are assigned different retention characteristics based on their functional requirements. Some groups maintain data during standby while others do not, allowing the system to optimize power consumption based on actual data retention needs of specific locations.

Inventive Principle:
Principle #3Local quality

4Device complexity

If fixed size relation between retention and non-retention SRAM parts is used, then circuit design is simplified, but adaptability during operation is reduced

Engineering Contradiction:
Improvecircuit designVSAvoidadaptability during operation
Core Design Contradiction:
Device complexityVSAdaptability or versatility

Solution Approach 1:

The patent implements dynamic control of retention mode through control logic that can switch between retention and non-retention states based on operational requirements. This dynamic adjustment allows the system to optimize between leakage current and operating speed depending on the current operational context.

Inventive Principle:
Principle #15Dynamics

Data Source

PatentUS7804732B2Memory control with selective retention
Publication Date: 2010.09.28 TELEFONAKTIEBOLAGET LM ERICSSON (PUBL)
  • US7804732B2 patent drawing
  • US7804732B2 patent drawing
  • US7804732B2 patent drawing

AI summary

The present invention relates to a memory circuit and a method of controlling data retention in the memory circuit, wherein a supply signal is selectively switched to a respective one of at least two virtual supply lines (24) each shared by a respective one of a plurality of groups (30-1 to 30-n) of memory cells (C0,0 to Cy,z). The selective switching is controlled based on a global activity control signal (A), used for setting the memory circuit either into a standby state or into an active state, and a local data retention indication signal (DR1 to DRn) allocated to a dedicated group of memory cells. Thereby, the data retention part of the memory circuit can be adapted to the application and its state, and standby mode leakaged power is only dissipated in those memory cells for which data retentions actually required.