Sequential SRAM Self-Repair Using Reordered Column Access
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Solution Overview
Problem
Conventional SRAM devices face functional and parametric failures due to faulty or slow bit cells, which existing repair techniques often address at the cost of increased device overhead and power consumption, posing challenges for low-power, high-performance applications in virtual and augmented reality systems.
Innovation Solution
The implementation of a self-repair system for SRAM devices that rearranges the sequential order of bit cell access, utilizes redundant columns, and employs a look-up table to map faulty bit cells to redundant ones, along with delayed memory access operations to accommodate slower bit lines, thereby reducing power consumption and device overhead.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional repair techniques are used to address faulty or slow bit cells, then reliability is improved, but device overhead and power consumption increase
Solution Approach 1:
The SRAM device performs self-diagnosis and self-repair through integrated test circuits and repair logic that automatically detect faulty bit cells and redirect access to redundant cells without external intervention, reducing the need for additional power-consuming repair mechanisms
Solution Approach 2:
Redundant bit cells are pre-configured and mapped during manufacturing testing, creating a lookup table that enables rapid redirection of access paths when failures occur, avoiding the need for complex real-time diagnosis and repair operations that would consume additional power
2Reliability
If conventional repair techniques are used to address faulty or slow bit cells, then reliability is improved, but device complexity increases
Solution Approach 1:
The repair functionality is merged with the existing SRAM structure by integrating test circuits, repair logic, and redundant cells within the same device architecture, eliminating the need for separate repair mechanisms and reducing overall device complexity
Solution Approach 2:
The redundant bit cells serve multiple functions: they can replace faulty cells, provide additional storage capacity, and assist in self-diagnosis operations, maximizing the utility of the added components while minimizing the need for dedicated repair structures
3Productivity
If bit cells are accessed in physical sequential order, then device simplicity is maintained, but access speed is limited by slower bit lines
Solution Approach 1:
The column access sequence is made dynamic and reconfigurable through control logic that can adjust the order of bit line activation based on performance characteristics, allowing the system to optimize for speed by accessing faster bit lines first while maintaining adaptability to different operational conditions
Solution Approach 2:
The access pattern parameter is changed from fixed physical sequential order to a variable order determined by bit line performance characteristics, enabling the system to bypass slow bit lines and prioritize faster ones, thereby improving overall access speed without fundamentally changing the physical structure
Data Source
AI summary
In some embodiments, a system comprises a static random access memory (SRAM) device and a controller. The SRAM device comprises a bit cell array comprising a plurality of bit cells arranged in a plurality of rows and a plurality of columns, each column operatively coupled to a pair of bit lines, wherein the plurality of columns is arranged as a plurality of column groups each comprising a plurality of local columns. The SRAM device further comprises a plurality of column decoders, each associated with a column group of the plurality of column groups. In some embodiments, the controller may be configured to read the local columns included in the column group by, for a given local column, sensing a voltage difference on a corresponding pair of bit lines, in a rearranged sequential order that is different from a physical sequential order of the plurality of local columns.