SRAM Bit Cell With Separate Read And Write Paths
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Solution Overview
Problem
As technology scales, the reduced supply voltages in SRAMs lead to decreased static noise margin, resulting in reduced efficiency for reading and writing bit cells due to unscaled threshold voltages of transistors.
Innovation Solution
Implementing separate read and write paths for each bit cell in SRAM, allowing transistors to be optimized for specific operations, and precharging bit lines to an intermediate voltage for reduced power consumption during reads.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by stationary object
If supply voltage is reduced to enable technology scaling, then power consumption is reduced, but static noise margin is reduced resulting in reduced reading and writing efficiency
Solution Approach 1:
The patent divides the SRAM bit cell into separate read and write paths with distinct transistor sets. The write path uses transistors (e.g., write access transistors) optimized for data insertion, while the read path uses different transistors (e.g., read access transistors) optimized for data sensing. This segmentation allows each path to be independently optimized for its function, maintaining reading/writing efficiency even at reduced supply voltages where traditional shared-path designs would fail.
2Productivity
If separate read and write paths are implemented, then static noise margin is increased improving read and write efficiency, but device complexity is increased
Solution Approach 1:
The patent merges the read and write functionality into a single unified bit cell structure that shares common elements such as the latch circuitry and bit lines. By combining functions that were traditionally separated into different cell structures, the design achieves the noise margin benefits of separate paths while avoiding the full complexity penalty of completely independent read and write cells. The shared architecture reduces transistor count and area overhead.
3Productivity
If transistors are optimized for specific operations in separate paths, then operational efficiency is improved, but manufacturing precision requirements are increased
Solution Approach 1:
The patent applies local quality by giving different transistor optimization characteristics to different regions of the bit cell. Write access transistors are sized and configured for strong drive capability to force data into the latch, while read access transistors are optimized for high input impedance and low leakage to enable sensitive detection. This localized optimization allows each transistor to be tuned for its specific function without requiring all transistors in the cell to meet the same stringent specifications, thereby reducing overall manufacturing precision requirements.
Data Source
AI summary
A method is for reading a first bit cell of a static random access memory in which the static random access memory has a first plurality of bit cells including the first bit cell. Each bit cell of the first plurality of bit cells includes a cross coupled pair of inverters for storing a logic state, optimized for being written, and powered by a read voltage during a read of the first plurality of bit cells. Each bit cell of the first plurality of bit cells is coupled to a true read bit line and a true write bit line, and a second plurality of bit cells is coupled to a complementary read bit line and a complementary write bit line. The true and complementary read bit lines are precharged to a precharge voltage of about half the read voltage. The true read bit line is predisposed to a logic low condition. One of a group consisting of a high impedance from the first bit cell to indicate that the logic state is a logic low and a signal voltage greater than the intermediate voltage to indicate that the logic state is a logic high is output from the first bit cell to the true read bit line.