4CPP FinFET SRAM Layout With Shared Bit Lines and Simpler Routing
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Solution Overview
Problem
The manufacturing of 4Cpp FinFET SRAM architectures faces challenges such as congested metal layers and the need for extra processing steps due to shared contacts and fin cuts, which complicate the routing of bit lines and increase complexity in the backend-of-line (BEOL) metal layer design.
Innovation Solution
A 4Cpp FinFET SRAM architecture that eliminates the need for fin cuts and shared contacts, allowing for simplified metal layer routing by sharing bit lines and complementary bit lines between cells, reducing the complexity and cost of processing and manufacturing.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If 4Cpp FinFET architecture is used, then transistor density is improved, but metal layer congestion increases and routing complexity worsens
Solution Approach 1:
The patent introduces a second metal layer (M2) to resolve the routing congestion in the first metal layer (M1). By moving word line connections to M2, the patent creates a three-dimensional interconnect architecture that allows M1 to be dedicated to bit line routing, thereby eliminating routing conflicts and reducing metal layer complexity while maintaining high transistor density.
2Ease of manufacture
If shared contacts are implemented, then manufacturing steps are reduced, but metal layer routing complexity increases
Solution Approach 1:
The patent segments the interconnect functions by dedicating M1 to bit line connections and M2 to word line connections. This segmentation allows shared contacts to be used effectively without increasing routing complexity, as each metal layer has a specific function. The segmentation resolves the contradiction by organizing the metal layer design to accommodate shared contacts while maintaining routing simplicity.
3Adaptability or versatility
If fin cuts are performed, then shared contacts are enabled, but additional processing steps are required
Solution Approach 1:
The patent performs fin cuts during the front-end-of-line (FEOL) process before backend-of-line (BEOL) metal layer formation. By completing the fin cuts early in the manufacturing sequence, the patent enables shared contact formation without adding steps to the BEOL process. This preliminary action maintains manufacturing efficiency while achieving the adaptability of shared contacts.
4Quantity of substance
If first metal layer is used for both bit lines and word lines, then interconnect density is improved, but routing congestion increases
Solution Approach 1:
The patent transitions from a two-dimensional routing scheme to a three-dimensional interconnect architecture by utilizing vertical stacking of metal layers. M1 is dedicated to bit line routing in the horizontal plane, while M2 carries word line connections, effectively using the vertical dimension to resolve routing congestion. This dimensional change maintains high interconnect density while eliminating routing conflicts.
Data Source
AI summary
A static random access memory (SRAM) cell includes a four-contact polysilicon pitch (4Cpp) fin field effect transistor (FinFET) architecture including a first bit-cell and a second bit cell. The SRAM cell includes a first bit line and a first complementary bit line, wherein the first bit line and the first complementary bit line are shared by the first and second bit-cells of the SRAM cell. The SRAM cell includes a first word line connected to the first bit cell, and a second word line connected to the second bit cell.