SRAM Cell Layout With Shared Channels and Layered Bit-Lines
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Solution Overview
Problem
The increasing complexity and density of semiconductor integrated circuits (ICs) lead to higher power dissipation and resistance issues, particularly in SRAM cells, due to shrinking metal line dimensions, which impede processing power and speed.
Innovation Solution
The implementation of non-rectangular SRAM cell shapes, such as L-shaped profiles, allowing adjacent cells to abut and share channel layers, combined with strategic metal line layering to reduce resistance and capacitance, where write bit-lines are placed in higher layers and read bit-lines in lower layers to improve operational efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If metal line dimensions are shrunk to increase functional density, then production efficiency is improved, but resistance and power dissipation increase
Solution Approach 1:
The patent applies dimensionality change by routing bit-lines through multiple metal layers (first bit-line in first metal layer, second bit-line in second metal layer) instead of relying on a single layer. This vertical stacking approach reduces the horizontal routing distance and resistance while maintaining high functional density, directly addressing the contradiction between increased density and increased resistance.
2Productivity
If metal line dimensions are shrunk to increase functional density, then production efficiency is improved, but power dissipation increases
Solution Approach 1:
The patent reduces power dissipation by utilizing multiple metal layers for bit-line routing. The first bit-line is positioned in a lower metal layer while the second bit-line is in a higher metal layer, creating a vertical routing path that reduces the effective resistance and current density in any single layer, thereby lowering overall power dissipation while maintaining high functional density.
3Productivity
If SRAM cells are designed with non-rectangular shapes to increase density, then functional density is improved, but cell stability may be affected
Solution Approach 1:
The patent employs asymmetry by designing SRAM cells with non-rectangular shapes where adjacent cells have different orientations (e.g., first SRAM cell with first orientation, second SRAM cell with second orientation perpendicular to the first). This asymmetric arrangement allows cells to abut efficiently and share channel layers, increasing functional density while maintaining cell stability through proper geometric configuration.
Data Source
AI summary
A method includes forming a first channel pattern on a substrate from a top view; forming first and second gate patterns extending across the first channel pattern; forming first, second, and third source/drain patterns on the first channel pattern, the first and second source/drain patterns on opposite sides of the first gate pattern and the second and third source/drain patterns on opposite sides of the second gate pattern, wherein a first channel region of the first channel pattern, the first gate pattern, and the first and second source/drain patterns form a first read pull-down transistor of a first static random access memory (SRAM) cell, and a second channel region of the first channel pattern, the second gate pattern, and the second and third source/drain patterns form a second read pull-down transistor of a second SRAM cell.