SRAM Cell Layout Using Shared Gate and Protruding Active Regions
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Solution Overview
Problem
SRAM cells require a balance between reducing size and maintaining performance, as they occupy larger areas compared to DRAM cells while needing to operate at higher speeds without refresh operations.
Innovation Solution
The semiconductor device design includes specific arrangements of NMOS and PMOS active regions, gates, and doped regions in a semiconductor substrate, where channel regions and doped regions are strategically formed to protrude and overlap, optimizing the layout to increase channel widths and reduce chip area without degrading performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of moving object
If the SRAM cell uses conventional layout with separate active regions for NMOS and PMOS transistors, then the device performance is maintained, but the chip area occupied is large
Solution Approach 1:
The patent merges the NMOS and PMOS active regions by making them adjacent and sharing a common gate structure. The second active region is positioned directly adjacent to the first active region, allowing both transistor types to share the same gate electrode, thereby reducing the overall chip area while maintaining proper electrical isolation through doped regions.
Solution Approach 2:
The patent implements nesting by having the second active region protrude into the first active region's area. Specifically, the second active region extends in the first direction to overlap with the gate structure, effectively nesting one active region within the spatial footprint of the other, which optimizes area utilization.
2Reliability
If the channel width is increased to improve cell current, then the operating performance is enhanced, but the chip area increases
Solution Approach 1:
The patent utilizes the vertical dimension by having the second active region protrude in the first direction (horizontal) while maintaining proper spacing in the second direction (vertical). This dimensional optimization allows the channel width to be effectively increased through strategic positioning rather than simple expansion, improving cell current without linearly increasing area.
Solution Approach 2:
The patent applies local quality by creating asymmetric doping concentrations within the active regions. Low-concentration doped regions are positioned at specific locations to enhance carrier concentration and mobility in critical areas, thereby improving cell current locally without requiring a uniform increase in overall channel dimensions.
Data Source
AI summary
A semiconductor device includes a first and a second active regions having a first conductive type and a second conductive type, respectively, being arranged in a first direction; a gate extending in the first direction; a first and a second channel regions defined under the gate in the first and the active regions, respectively; a first low-concentration doped region, having the second conductive type, formed at sides of the gate in the first active region and a first high-concentration doped region, having the second conductive type, formed at sides of the first low-concentration doped region in the first active region; and a second low-concentration doped region, having the first conductive type, formed at sides of the gate in the second active region and a second high-concentration doped region, having the first conductive type, formed at sides of the second low-concentration doped region in the second active region.