Two-Port SRAM Layout With Shared Read Bit-Lines
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Solution Overview
Problem
As semiconductor devices continue to be scaled down, interconnection routing for semiconductor devices uses too many routing resources, impacting cell scaling and memory performance.
Innovation Solution
The implementation of gate-all-around (GAA) transistors with a compact two-port SRAM cell design, where metal conductors are strategically positioned in different layers to reduce capacitance and resistance, and adjacent SRAM cells share read bit-lines to minimize routing complexity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If conventional interconnection routing is used in scaled-down semiconductor devices, then routing resources are consumed excessively, but cell scaling and memory performance are degraded
Solution Approach 1:
The patent implements gate-all-around (GAA) transistors with gates that wrap completely around the channel in three dimensions, transitioning from conventional planar two-dimensional gating to three-dimensional surrounding gating. This dimensional change provides superior gate control over the channel, enabling better performance at scaled dimensions while reducing the routing resources needed for interconnections.
Solution Approach 2:
The patent divides the semiconductor device into distinct functional regions including memory cells, logic circuits, and interconnection layers, with each region optimized independently. The interconnection routing is segmented into multiple metal layers, allowing complex routing functions to be distributed across layers rather than concentrated in a single plane, thereby reducing overall routing complexity.
2Ease of operation
If more routing resources are allocated for interconnection, then connectivity is improved, but cell area increases and scaling is impacted
Solution Approach 1:
By implementing three-dimensional gate-all-around structures, the patent achieves enhanced control and connectivity functions within a compact footprint. The vertical stacking and surrounding gate configuration provide multiple conduction paths and control points without expanding the lateral cell area, maintaining scalability while improving interconnection capabilities.
Solution Approach 2:
The patent utilizes three-dimensional gate structures that surround the channel on multiple sides, creating a porous-like surrounding configuration that provides comprehensive control over the channel from all directions. This surrounding gating approach improves connectivity and control efficiency while maintaining a compact cell area.
Data Source
AI summary
A semiconductor device includes a first static random access memory (SRAM) cell, a second SRAM cell, and a first and a second gate end dielectric structures. The first SRAM cell includes a first write port including a first write-port pass-gate (WPG) transistor, a second WPG transistor, a first write-port pull-down (WPD) transistor, and a second WPD transistor, and a first read port including a first read-port pull-down (RPD) transistor and a first read-port pass-gate (RPG) transistor. The second SRAM cell includes a second write port including a third WPG transistor, a fourth WPG transistor, a third WPD transistor, and a fourth WPD transistor, and a second read port including a second RPD transistor and a second RPG transistor. The first gate end dielectric structure is between the first write-port and the first read-port. The second gate end dielectric structure is between the second write-port and the second read-port.