SRAM Dynamic Power Reduction via Shared Sense Amplifiers
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Solution Overview
Problem
Conventional SRAM designs face challenges in reducing dynamic power consumption and propagation delays in signal communication, leading to increased complexity and cost, especially in systems with multiple receivers and bit cells, where leakage currents and power management inefficiencies hinder performance.
Innovation Solution
The proposed solution involves a circuit design for SRAM that includes shared memory bank signal lines, a bridge circuit connecting memory bank and memory block signal lines, and shared sense amplifiers across memory banks, along with a controller for bit cell access, which reduces dynamic power through charge sharing and efficient signal transmission mechanisms.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If conventional SRAM designs use separate column multiplexors for each memory bank, then each memory bank can be accessed independently, but the device complexity and power consumption increase significantly
Solution Approach 1:
The patent merges the column multiplexing function from individual memory banks into a single shared column multiplexor at the memory block level. This consolidation reduces the total number of multiplexors needed while maintaining the ability to access any memory bank through the shared resource, thereby reducing device complexity without sacrificing independent access capability.
Solution Approach 2:
The shared column multiplexor is designed to handle signals from multiple memory banks universally. Instead of having dedicated multiplexors for each bank, a single multiplexor structure serves multiple banks by selecting the appropriate bank based on address decoding, making the system more efficient and less complex.
2Reliability
If conventional SRAM designs use individual sense amplifiers for each memory bank, then signal detection is reliable, but the device complexity and area increase
Solution Approach 1:
The patent combines sense amplifiers into a shared resource at the memory block level rather than having dedicated sense amplifiers for each memory bank. The shared sense amplifiers are activated only when needed for specific memory bank accesses, reducing the total number of sense amplifiers required while maintaining reliable signal detection through proper timing and control.
3Speed
If stronger drivers are used at the transmitter to reduce propagation delay, then signal transmission speed improves, but power consumption increases
Solution Approach 1:
The patent changes the voltage swing parameter in the SRAM circuit to reduce dynamic power consumption. By minimizing unnecessary voltage swings during signal transitions and using controlled voltage levels in the memory circuitry, the design achieves faster operation with lower power consumption, resolving the trade-off between speed and energy use.
4Speed
If more buffers are added to reduce propagation delay in signal lines, then signal strength is maintained, but the device complexity and area increase exponentially
Solution Approach 1:
The patent merges buffer functions into the memory bank signal line structure rather than adding separate buffer stages. The memory bank signal lines are designed with inherent buffering capabilities through their connection to the shared column multiplexor and sense amplifier structures, reducing the need for additional discrete buffers while maintaining signal strength and minimizing propagation delay.
Data Source
AI summary
A circuit for reducing dynamic power in SRAM and methods for using the same are disclosed. In one embodiment, a circuit for reducing dynamic power in SRAM includes a plurality of memory blocks, which includes a plurality memory banks, which in turn includes a plurality bit cells; a set of memory bank signal lines; a set of memory block signal lines shared across the plurality of memory banks in the memory block; a bridge circuit couple between the set of memory bank signal lines and the set of memory block signal lines; a set of sense amplifiers corresponding to the set of memory block signal lines, where the set of sense amplifiers are shared among the plurality of memory banks in the memory block; and a controller configured to control an access of one or more bit cells in the plurality bit cells.