SRAM Cell With Shift I/O for Concurrent Data Updates
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Solution Overview
Problem
Conventional SRAM technologies face high latency and power consumption due to row-by-row read-modify-write operations, limiting their ability to handle high concurrent update requests effectively, especially in data-intensive applications like neural networks.
Innovation Solution
A static random-access memory design incorporating a dual-inverter circuit with switch-controlled bit-lines and word-lines, allowing for high-concurrency data access and update through shift-input and shift-output operations, enabling efficient data processing with low power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If row-by-row read-modify-write method is used in conventional SRAM, then data access is performed sequentially, but latency and power consumption increase due to frequent bit-line charges and repeated read-write operations
Solution Approach 1:
The patent segments the bit-line charging operation into selective column-based charging instead of charging all bit-lines in a row. Only the bit-lines corresponding to the target column are charged, while other bit-lines remain in high-impedance state. This segmentation eliminates unnecessary charging operations and reduces both latency and power consumption in read-modify-write operations
Solution Approach 2:
The patent dynamically controls the switching between row address selection and column address selection based on the operation mode. The bit-line drivers are dynamically enabled or disabled according to whether a read or write operation is being performed on the selected column, optimizing the timing and power consumption of each operation cycle
2Productivity
If general-purpose SRAM increases the number of arrays to improve parallelism, then concurrent update requests can be handled better, but serious overhead is introduced to peripheral circuits
Solution Approach 1:
The patent makes the SRAM array universal by enabling it to handle both row-based and column-based operations through the same physical array structure. The novel addressing mechanism allows the same array to serve multiple functions: traditional row-by-row operations, column-selective operations, and concurrent update requests, eliminating the need for multiple dedicated arrays and reducing peripheral circuit overhead
Solution Approach 2:
The patent introduces column-based addressing as a new dimension of operation alongside the traditional row-based addressing. This adds a vertical dimension to the conventional horizontal row-by-row access pattern, enabling concurrent operations by accessing different columns simultaneously within the same row, thereby improving parallelism without increasing the number of arrays
3Ease of operation
If bit-lines are precharged with power supply voltage and zero voltage to drive columns, then write operations can be performed, but power consumption increases due to frequent charging and discharging
Solution Approach 1:
The patent applies local quality by charging only the specific bit-lines that are needed for the current write operation, rather than precharging all bit-lines in the selected row. The bit-line drivers are selectively enabled based on the column address, so only the local bit-lines corresponding to the target column are charged to the required voltage levels, significantly reducing overall power consumption while maintaining full write operation capability
Data Source
AI summary
The present disclosure relates to a static random-access memory and an electronic device. The memory includes at least one storage circuit, wherein the storage circuit includes a first inverter, a second inverter, a first switch, a second switch, a third switch, a fourth switch, a fifth switch, a word-line, a first bit-line, a second bit-line, a shift-input line, and a shift-output line. The circuit is used to access data by using the first bit-line and/or the second bit-line when it works in a first mode, and the circuit is used to shift the input data to the shift-input line and output the shifted data through the shift-output line when it works in a second mode. By implementing shift-input and shift-output within the memory, the disclosed embodiment can achieve high-concurrency data access and data update, and it also enables high integration and low power consumption.