Single Cycle Data Copy in Two-Port SRAM Using Local Evaluation Circuit
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Solution Overview
Problem
Current domino SRAMs face challenges in rapidly copying data from one memory cell to another within a single cycle, which is critical for applications like three-dimensional graphics processing where speed is essential for system performance.
Innovation Solution
The proposed SRAM design includes a local evaluation circuit with a global bit line and a copy signal, enabling data to be copied from any memory cell in a column to another within a single cycle by utilizing true and complement local bit lines, read local bit lines, and a global bit line, along with precharge devices and control signals to facilitate the copy operation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If traditional domino SRAM is used for data copying, then the structure is simple, but the data copying speed is insufficient for single-cycle operations
Solution Approach 1:
The bit line circuit is segmented into multiple independent bit line buffers (first bit line buffer, second bit line buffer, third bit line buffer, fourth bit line buffer) that can operate in parallel. Each buffer handles specific bit line connections, allowing simultaneous data copying from multiple memory cells to different destinations within a single cycle, thereby increasing copying speed while maintaining manageable circuit complexity through modular organization
Solution Approach 2:
The bit line buffers are designed to handle multiple functions: they can connect memory cells to different bit lines, support both read and write operations, and enable data copying between any two memory cells in the column. This multi-functionality allows a single buffer structure to replace what would otherwise require multiple dedicated circuits, achieving high-speed single-cycle copying without proportionally increasing complexity
2Loss of time
If data copying is performed in multiple cycles, then the circuit complexity is reduced, but the time required for data transfer increases
Solution Approach 1:
The bit line buffers enable continuous data copying operations within a single clock cycle by maintaining active connections between memory cells and bit lines throughout the entire cycle. The buffers prevent interruption of the copying process, allowing data to be transferred continuously from source to destination cells without requiring multiple discrete cycles, thus minimizing data transfer time and maximizing copying throughput
Data Source
AI summary
A static random access memory (SRAM) includes a column of SRAM memory cells. The SRAM may include a circuit to copy a value stored in any SRAM memory cell in a column of SRAM memory cells to any SRAM memory cell in the column of SRAM memory cells in a single cycle of the SRAM.