SRAM Static Noise Margin Test Structure On-Chip
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Solution Overview
Problem
Current methods for assessing the static noise margin (SNM) of SRAM memory cells are time-consuming and inefficient, particularly at lower supply voltages, due to the need for extensive measurement and post-processing of voltage transfer 'butterfly curves', which is prohibitive in production test environments.
Innovation Solution
The implementation of discrete point measurement structures on-chip or within scribe lines, allowing for the assessment of SNM through four single-point measurements using half-bit test structures, eliminating the need for time-consuming butterfly curve acquisition and post-processing.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If voltage transfer butterfly curves are used to assess SNM, then measurement accuracy is improved, but measurement time and processing complexity increase significantly
Solution Approach 1:
The patent extracts only the critical data points needed for SNM assessment from the complete butterfly curve measurement. Instead of measuring and processing the entire voltage transfer curve, the invention identifies and measures specific key points (such as the intersection point and critical voltage levels) that directly determine SNM. This extraction approach maintains measurement accuracy while dramatically reducing the time and computational resources required for post-processing.
Solution Approach 2:
The patent segments the complex butterfly curve measurement into discrete, independent measurement points. Rather than treating SNM assessment as a continuous curve analysis problem, the invention divides it into separate point measurements that can be taken independently. This segmentation allows for faster measurement acquisition and simplifies the assessment process by focusing only on the critical points that define SNM boundaries.
2Measurement precision
If extensive measurement and post-processing of butterfly curves is performed, then SNM assessment accuracy is improved, but productivity in production test environments deteriorates
Solution Approach 1:
The patent extracts only the essential measurement points required for SNM determination from the full butterfly curve. By taking out just the critical data points (such as threshold voltages and intersection points) rather than measuring the complete curve, the invention maintains sufficient assessment accuracy while enabling much faster measurement cycles that are compatible with high-volume production testing environments.
Solution Approach 2:
The patent applies partial action by measuring only the necessary portion of the voltage transfer characteristics needed for SNM assessment. Instead of performing exhaustive measurements of the entire butterfly curve, the invention measures just enough data points to accurately determine SNM, thereby achieving the minimum required action for reliable assessment while maximizing productivity.
3Speed
If discrete point measurement structures are used, then measurement speed is improved, but measurement complexity decreases
Solution Approach 1:
The patent implements self-service through on-chip test structures that are integrated directly into the SRAM array. These discrete point measurement structures are designed to be self-contained, requiring minimal external test equipment and automated measurement sequences. The on-chip structures perform the critical measurements internally, reducing the complexity of external test setup and enabling faster measurement speeds while maintaining simplicity in the overall test system.
Data Source
AI summary
A set of memory cell test structures and a method for assessing of the static noise margin (SNM) of a memory cell or cells, using discrete point measurement structures provided either on-chip or within the scribe lines. A set of memory structures may comprise first and second test structures, individually comprising a memory cell, having one or more left and right half-bit test structures having hard-wired connections between select nodes of each memory cell half-bit and one or more voltage supplies. The half-bits of the first test structure are configured for measuring respective left and right standby SNM values, and the half-bits of the second test structure are configured for measuring respective left and right cell ratio values at respective output nodes of the structures, using applied supply voltages for on-chip assessment of the static noise margin of the memory cells.