SRAM Static Noise Margin Measurement via Transmission Gate Access

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Solution Overview

Problem

Current methods for measuring the static noise margin (SNM) of SRAM cells are inaccurate, indirect, or time-consuming, particularly when dealing with large numbers of cells, and do not allow for easy setup, which is problematic in environments requiring high reliability such as space or high radiation conditions.

Innovation Solution

The development of direct measurement test structures using transmission gates that provide flexible and direct access to SRAM internal nodes, allowing for the measurement of SNM in a short time and with a simple setup, without the need for additional measurement cells, and enabling the measurement of read, write, and hold SNM for large numbers of SRAM bits.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Ease of manufacture

If traditional simulation techniques are used to determine SNM, then measurement setup is simple, but measurement accuracy is insufficient for all operating conditions

Engineering Contradiction:
Improvemeasurement setup simplicityVSAvoidSNM measurement accuracy
Core Design Contradiction:
Ease of manufactureVSMeasurement precision

Solution Approach 1:

The patent introduces transmission gates as intermediary components that provide direct access to internal SRAM nodes. These transmission gates act as controlled switches that allow external measurement equipment to probe internal node voltages without disrupting the SRAM cell operation, thereby achieving accurate measurements while maintaining setup simplicity.

Inventive Principle:
Principle #24Intermediary (Mediator)

Solution Approach 2:

The test structure incorporates multiple transmission gates that can be configured to access different internal nodes of the SRAM cell. This universal access capability allows the same test structure to measure various parameters (read SNM, write SNM, hold SNM) under different operating conditions, eliminating the need for multiple specialized measurement setups.

Inventive Principle:
Principle #6Universality (Multi-functionality)

2Device complexity

If indirect measurement techniques through probing points are used, then device complexity is reduced, but measurement effectiveness is insufficient

Engineering Contradiction:
Improvemeasurement structure complexityVSAvoidSNM measurement effectiveness
Core Design Contradiction:
Device complexityVSReliability

Solution Approach 1:

The patent segments the SRAM cell measurement into multiple independent access paths, each controlled by a dedicated transmission gate. This segmentation allows selective access to specific internal nodes (e.g., Q, QB, bit lines) without interfering with other parts of the cell, enabling reliable indirect measurements while keeping the overall structure relatively simple.

Inventive Principle:
Principle #1Segmentation

3Quantity of substance

If current measurement approaches are used for large numbers of SRAM cells, then measurement coverage is limited, but measurement time is excessive

Engineering Contradiction:
Improvenumber of SRAM cells measurableVSAvoidmeasurement time
Core Design Contradiction:
Quantity of substanceVSLoss of time

Solution Approach 1:

The test structure design uses universal transmission gate configurations that can be replicated across multiple SRAM cells. This allows the same measurement methodology to be applied to large arrays of cells systematically, enabling high-throughput measurement of many cells without requiring different approaches for each cell, thereby reducing total measurement time.

Inventive Principle:
Principle #6Universality (Multi-functionality)

Data Source

PatentEP3719804B1Direct measurement test structures for measuring static random access memory static noise margin
Publication Date: 2024.07.10 THE BOEING CO
  • EP3719804B1 patent drawingFigure 1
  • EP3719804B1 patent drawingFigure 2
  • EP3719804B1 patent drawingFigure 3

AI summary

A test structure for measuring static noise margin (SNM) for one or more static random access memory (SRAM) cells can include a first transistor gate (TG) and a second TG electrically coupled to each SRAM cell. In an implementation, an interconnect between an output of a first inverter and an input of a second inverter of the SRAM cell can be electrically disconnected using a cut off. During operation of the SRAM cell, internal storage nodes within the SRAM cell can be electrically coupled through the first TG and the second TG to, for example, external pins and to a test fixture. Electrical parameters such as voltage can be measured at the internal storage nodes through the external pins and used to calculate SNM of the SRAM cell.