SRAM Soft Failure Repair via Dynamic Voltage Adjustment
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Solution Overview
Problem
SRAM memory cells often experience failures due to both hard and soft failure mechanisms, with soft failures being particularly challenging as they can arise from voltage conditions during read and write cycles, leading to increased costs due to the need for redundancy in IC design.
Innovation Solution
The method involves identifying and correcting soft failures in SRAM arrays using selective circuit techniques that adjust voltages on word lines and bit lines during write and read cycles, such as boosting word line voltages, lowering VDD voltage, and lowering bit lines below VSS, to repair memory cells without requiring additional redundant cells.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If redundant memory cells are added to replace failed memory cells, then reliability is improved, but area usage increases and cost increases
Solution Approach 1:
The patent applies parameter changes by modifying voltage conditions during read and write cycles to correct soft failures. Specifically, it adjusts word line voltage, bit line voltage, and VDD voltage levels dynamically during operation to overcome threshold voltage variations and leakage current issues, thereby improving reliability without adding redundant cells
Solution Approach 2:
The patent implements self-service by enabling the memory array to self-correct soft failures through automated voltage adjustments during read and write cycles. The system detects and corrects its own errors by dynamically modifying operating parameters without requiring external intervention or additional hardware redundancy
2Reliability
If redundant memory cells are added to replace failed memory cells, then reliability is improved, but IC cost increases
Solution Approach 1:
The patent uses parameter changes to modify voltage conditions during memory operations to correct soft failures. By dynamically adjusting word line, bit line, and VDD voltages, the system improves reliability without incurring the additional costs associated with manufacturing redundant memory cells
3Reliability
If voltage conditions are adjusted during read and write cycles, then soft failures are corrected, but device complexity increases
Solution Approach 1:
The patent applies dynamics by making voltage conditions adjustable and adaptive during read and write cycles. The system dynamically modifies word line, bit line, and VDD voltages based on detected failure conditions, transforming a static memory system into one that can adapt its operating parameters to correct soft failures
Solution Approach 2:
The patent implements parameter changes by modifying voltage levels during memory operations to correct soft failures. Specifically, it adjusts word line voltage, bit line voltage, and VDD voltage dynamically during read and write cycles to overcome threshold voltage variations and leakage current issues
Data Source
AI summary
An embodiment of the invention provides a method of repairing soft failures in memory cells of an SRAM array. The SRAM array is tested to determine the location and type of soft failures in the memory cells. An assist circuit is activated that changes a voltage in a group of memory cells with the same type of soft failure. The change in voltage created by the assist circuit repairs the soft failures in the group. The group may be a word line or a bit line. The type of soft failures includes a failure during a read of a memory cell and a failure during the write of a memory cell.