SRAM Cell Dynamic Split Ground and Wordline for Stability
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Solution Overview
Problem
SRAM stability degrades rapidly with scaled devices, and existing asymmetric designs compromise performance, density, and design assist overhead, limiting their usefulness for differential sensing and increasing complexity in low-power applications.
Innovation Solution
The SRAM cell design incorporates dynamic split ground (GND) and split wordline (WL) with separate vertical GND buses, allowing for enhanced stability and differential sensing, enabling both bitlines for read operations and independent GND shifts to optimize performance and power efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If asymmetric SRAM cell design is used to improve stability, then stability is enhanced, but the SRAM cell cannot serve as standard cell type and power down scheme becomes more complicated
Solution Approach 1:
The ground line is segmented into two separate ground lines (first ground line and second ground line) that can be independently controlled. This segmentation allows the SRAM cell to maintain asymmetric stability benefits while enabling flexible configuration for different operating modes including standard cell type operation and simplified power down schemes.
Solution Approach 2:
The ground lines are made dynamic through separate control mechanisms, allowing the ground potential to be adjusted independently on each side of the SRAM cell. This dynamic control enables the cell to adapt between asymmetric and symmetric operating modes, resolving the contradiction between stability enhancement and operational versatility.
2Area of stationary object
If device dimensions are continuously scaled to increase SRAM array area, then chip area utilization improves, but SRAM stability degrades rapidly
Solution Approach 1:
Different ground potentials are applied locally to different sides of the SRAM cell through the separate ground lines. This local quality adjustment compensates for the stability degradation caused by scaling, allowing each side of the cell to be optimized independently while maintaining overall cell functionality and enabling continued device scaling.
Data Source
AI summary
An SRAM cell with dynamic split ground (GND) and split wordline (WL) for extreme scaling is disclosed. The memory cell includes a first access transistor enabled by a first wordline to control access to cross coupled inverters by a first bitline. The memory cell further includes a second access transistor enabled by a second wordline to control access to the cross coupled inverters by a second bitline. The memory cell further includes a split ground line comprising a first ground line (GNDL) separated from a second ground line (GNDR). The GNDL is connected to a transistor of a first inverter of the cross coupled inverters and the GNDR is connected to a first transistor of a second inverter of the cross coupled inverters.