SRAM Split Write Control for Radiation Hardness
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Solution Overview
Problem
In radiation environments, SRAM cells are vulnerable to Single Event Upsets (SEUs) due to radiation-induced charge, and existing radiation-hardened SRAM designs face challenges in balancing radiation hardness with write time efficiency, as the delay element used for SEU prevention is disabled during writes, making other cells in the same row susceptible to errors.
Innovation Solution
Implementing a split write control mechanism where each memory word has a dedicated write-word line that carries delay and bypass signals, allowing only the memory word being written to have its delay bypassed, while others maintain enabled delays to prevent SEUs, thereby reducing the Soft Error Rate (SER).
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of time
If the delay element is disabled during write operations, then the write time of the cell is decreased, but other cells in the same row become susceptible to SEUs
Solution Approach 1:
The patent divides the control mechanism into separate dedicated write-word lines for each memory word, allowing independent control of the delay element in each cell. This segmentation enables selective bypassing of the delay element only in the specific cell being written, while maintaining delay protection in all other cells within the same row, thus resolving the contradiction between write speed and radiation hardness.
2Reliability
If the delay element is enabled to prevent SEU, then radiation hardness is improved, but the write time of the cell increases
Solution Approach 1:
The patent implements dynamic control of the delay element through dedicated write-word lines that can selectively enable or disable the delay based on whether a write operation is occurring in that specific cell. During write operations, the delay is dynamically bypassed in the target cell to reduce write time, while remaining enabled in other cells to maintain radiation hardness, thus dynamically optimizing both performance and reliability.
3Device complexity
If a single write-word line is shared across multiple memory words, then device complexity is reduced, but control precision over individual cell delay bypassing is lost
Solution Approach 1:
The patent segments the write-word line control into dedicated individual lines for each memory word, eliminating the need for complex decoding logic that would be required to selectively control individual cells using a shared line. This segmentation provides precise control over the delay element in each specific cell while maintaining simplicity in the control architecture, as each cell has its own dedicated control path.
Data Source
AI summary
A Static Random Access Memory (SRAM) having a split write control is described. The SRAM includes bit, write, and write-word lines. Each memory cell within the SRAM includes a delay which is coupled to a dedicated write-word line. When a cell is not being written, its delay receives a delay signal on its associated write-word line, which increases the response time of the cell. When a cell is to be written, however, its delay receives a bypass signal on its associated write-word line, which decreases the response time of the SRAM cell.