3-Port SRAM Structure With Stacked Read Transistors for Low Leakage

The patent implements gate-all-around (GAA) transistor structures where the gate electrode completely surrounds the channel region in three dimensions, transitioning from planar 2D gate control to 3D wraparound control. This dimensional change enables superior electrostatic control over the channel, reducing leakage current and power dissipation while maintaining high functional density achieved through scaling.

The patent employs complementary field-effect transistor (CFET) technology using stacked n-type and p-type transistor structures with different material compositions. The channel layers use different semiconductor materials (e.g., SiGe for one type, Si for another) with tailored properties to optimize carrier mobility and threshold voltage, enabling low-power operation while maintaining high density.

The patent divides the transistor structure into distinct segmented layers including channel layers, sacrificial layers, spacer layers, and gate electrode portions formed at different stages. The GAA structure is built by sequentially forming and removing sacrificial layers to create suspended channel regions, with spacers defining precise geometries. This segmentation enables complex 3D gate control while using standardized fabrication processes.

The patent employs sacrificial layers that are formed preliminarily to define the channel region geometry before the actual gate electrode is created. These sacrificial structures guide subsequent processing steps including spacer formation, etching, and gate deposition. The preliminary sacrificial structures are removed after serving their templating function, leaving the final GAA structure.