SRAM-Standard Cell Layout With Filler Cells for White Space Reduction
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Solution Overview
Problem
Conventional integrated circuits are not cost-effective in chip area usage due to the need for large white spaces between Static Random Access Memory (SRAM) cells and standard cells, as SRAM cells cannot abut standard cells directly, leading to inefficient use of space.
Innovation Solution
The introduction of filler cells with varying heights, designed to fit between SRAM cells and standard cells, allowing them to abut without violating design rules, thereby minimizing the spacing between SRAM arrays and standard cells, and optimizing chip area usage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If white space is reserved between SRAM cells and standard cells to satisfy design rules, then design rules are satisfied, but chip area usage efficiency deteriorates
Solution Approach 1:
Filler cells are introduced as intermediary elements between SRAM cells and standard cells. These filler cells act as mediators that satisfy the design rule requirement for spacing while minimizing the wasted space. The filler cells are strategically placed to abut both the SRAM cell column and the standard cell row, thereby eliminating the need for excessive white space while maintaining design rule compliance.
Solution Approach 2:
The invention changes the parameter of cell height by providing filler cells with different heights. By varying the height parameter of filler cells, the layout can be optimized to minimize white space while satisfying design rules. Different filler cell heights allow for flexible adaptation to different SRAM and standard cell configurations, maximizing chip area utilization.
2Area of stationary object
If SRAM cells abut standard cells directly to maximize space utilization, then chip area usage efficiency improves, but design rules are violated
Solution Approach 1:
Filler cells serve as necessary intermediaries that enable direct abutting of SRAM cells and standard cells while maintaining design rule compliance. Without these filler cells, direct abutting would violate design rules. The filler cells are minimally sized to provide just enough separation to satisfy design rules while allowing maximum space utilization.
3Reliability
If large white space is reserved between SRAM arrays and standard cells, then design and process rules are satisfied, but chip area waste increases
Solution Approach 1:
Filler cells are introduced as intermediary elements between SRAM arrays and standard cells to satisfy design and process rules while minimizing chip area waste. These filler cells are precisely sized and positioned to provide the minimum necessary separation, thereby eliminating excessive white space while maintaining rule compliance.
Solution Approach 2:
By providing filler cells with varying heights, the invention optimizes the spacing parameter to minimize wasted chip area. The height parameter of filler cells is adjusted to fit different layout configurations, ensuring that the white space between SRAM arrays and standard cells is minimized while still satisfying design and process rules.
Data Source
AI summary
A method includes laying out a standard cell region, with a rectangular space being within the standard cell region. The standard cell region includes a first row of standard cells having a first bottom boundary facing the rectangular space, and a plurality of standard cells having side boundaries facing the rectangular space. The plurality of standard cells include a bottom row of standard cells. A memory array is laid out in the rectangular space, and a second bottom boundary of the bottom row and a third bottom boundary of the memory array are aligned to a same straight line. A filler cell region is laid out in the rectangular space. The filler cell region includes a first top boundary contacting the first bottom boundary of the first row of standard cells, and a fourth bottom boundary contacting a second top boundary of the memory array.