SRAM Storage Array for Multithreaded High-Bandwidth Data Supply
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Solution Overview
Problem
Current techniques for storing registers in processor architecture are inefficient, expensive, and consume excessive power, making them unsuitable for energy and area-efficient storage and high-bandwidth data supply to function units.
Innovation Solution
A storage array utilizing static random-access memory (SRAM) with hierarchical multi-ported access, incorporating 8T SRAM cells and dedicated global read bit lines, allows for efficient conflict-free access patterns and reduced energy consumption by decoupling local and global bit line operations, enabling high-bandwidth data transfer within a multithreaded environment.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by moving object
If traditional register file techniques are used, then data storage is provided, but energy consumption is excessive and area efficiency is poor
Solution Approach 1:
The storage array is divided into multiple banks (e.g., bank 0, bank 1, bank 2, bank 3) that can be independently accessed. Each bank contains multiple words, allowing parallel access operations across different banks. This segmentation enables the system to achieve high bandwidth by simultaneously servicing multiple threads across different banks, thereby reducing per-operation energy consumption while maintaining storage capacity.
Solution Approach 2:
The patent introduces a hierarchical memory structure with multiple levels: L1 register files, L2 cache, and L3 cache. This vertical dimensionality allows the system to optimize for different access patterns - fast access to frequently used data in L1, moderate access to L2, and slower access to L3. This multi-level hierarchy reduces the energy cost of accessing data by keeping frequently accessed data in smaller, lower-power memory structures.
2Productivity
If larger storage arrays are implemented to support multithreading, then data supply bandwidth increases, but area cost increases prohibitively
Solution Approach 1:
Multiple thread contexts share the same physical storage resources through time-multiplexed access. The register file is designed to support concurrent access from multiple threads by using banked architecture where different threads can access different banks simultaneously. This merging of thread-specific logical registers into shared physical storage structures achieves high bandwidth for multithreading without proportionally increasing the physical area.
Solution Approach 2:
The storage array is designed with universal banks that can service multiple threads and multiple data types. Each bank can be accessed by any thread, and the same physical storage structure serves both as register file and cache memory at different hierarchy levels. This multi-functionality allows a single storage structure to provide high bandwidth for various operations without requiring separate dedicated storage for each function.
3Reliability
If more storage resources are allocated, then conflict-free access patterns improve, but power usage increases
Solution Approach 1:
The storage system dynamically allocates access resources based on actual thread activity and access patterns. The bank selection and memory hierarchy utilization are dynamically adjusted based on which threads are active and what data is being accessed. This dynamic behavior allows the system to provide conflict-free access when needed while entering lower-power states when full capacity is not required, avoiding constant high power consumption.
Data Source
AI summary
A system, method, and computer program product are provided for implementing a storage array. In use, a storage array is implemented utilizing static random-access memory (SRAM). Additionally, the storage array is utilized in a multithreaded architecture.