SRAM Strap Cell Design for RC Delay Reduction
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Solution Overview
Problem
The increasing complexity and miniaturization of Static Random Access Memory (SRAM) cells in semiconductor integrated circuits lead to higher sheet resistance in metal lines, resulting in increased RC delay, which hinders improvements in read and write speed.
Innovation Solution
The implementation of a SRAM array design that includes a strap cell with H-shaped N-type and P-type well regions and a deep N-type well, along with fin field-effect transistors, to reduce resistance and avoid latch-up issues, while maintaining uniform charge distribution and improved performance across the array.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If SRAM cells are miniaturized to increase functional density, then the number of interconnected devices per chip area increases, but the sheet resistance of metal lines increases and RC delay increases
Solution Approach 1:
The patent applies local quality by creating asymmetric well structures with different doping types (N-type and P-type wells) in different regions of the strap cell. The N-type well is positioned under one bit line connection while the P-type well is positioned under the other bit line connection, creating localized electrical characteristics that reduce resistance in specific current paths without affecting the entire array uniformly.
Solution Approach 2:
The patent extends the well structures vertically into deep N-type wells that penetrate through the substrate, adding a depth dimension to the well structures. This vertical extension creates additional current paths through the substrate, effectively reducing the horizontal resistance in miniaturized cells by providing alternative current flow routes in the vertical dimension.
2Area of stationary object
If metal line dimensions are reduced in miniaturized SRAM cells, then chip area decreases, but sheet resistance of metal lines increases
Solution Approach 1:
The patent introduces deep N-type wells as intermediary structures that mediate between the miniaturized metal lines and the substrate. These wells act as intermediate conductive paths that bridge the gap created by reduced metal line dimensions, providing low-resistance connections that compensate for the increased sheet resistance in scaled-down metal lines.
3Productivity
If SRAM cells are scaled down to increase density, then functional density increases, but RC delay increases
Solution Approach 1:
The patent segments the current path by creating separate N-type and P-type well regions that divide the current flow into distinct pathways. This segmentation allows current to flow through optimized paths in each well type, reducing the overall RC delay compared to a single continuous path in miniaturized cells.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This design enhances the read and write speed of SRAM cells by reducing resistance and avoiding latch-up problems, thereby improving the overall performance and efficiency of the SRAM array.
Implementation Method 1
fin field-effect transistors
Implementation Method 2
H-shaped N-type and P-type well regions
Implementation Method 3
deep N-type well
Data Source
AI summary
A SRAM array is provided. The SRAM array includes a first bit cell array and a second bit cell array arranged along a first direction, and a strap cell arranged along a second direction and positioned between the first bit cell array and the second bit cell array along the first direction. The strap cell includes a first P-type well region, two first N-type well regions, a second N-type well region. The two first N-type well regions are separated by the first P-type well region in the first direction, and the second N-type well region and one of the two first N-type well regions are separated by the first P-type well region in the second direction. The strap cell further includes a deep N-type well region underlying the two first N-type well regions and the second N-type well region.