SRAM Array Sub-Array Segmentation for Bit-Line RC Delay Reduction
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Solution Overview
Problem
The increasing sheet resistance of metal lines in SRAM cells leads to higher RC delay, making it difficult to improve read and write speeds, especially as SRAM cells are scaled down, and the larger size required to enhance efficiency results in increased bit-line metal coupling capacitance and longer word-lines, reducing differential speed and worsening resistance.
Innovation Solution
The SRAM array is divided into sub-arrays with jumper structures connecting bit-lines and word-lines differently, reducing load on bit-lines and sense amplifiers, and using a double word-line scheme to decrease resistance and RC delay, while separate CVdd lines provide power efficiently to each sub-array.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of moving object
If SRAM cells are down-scaled to increase integration density, then area is reduced, but sheet resistance of metal lines increases causing higher RC delay
Solution Approach 1:
The bit-line is divided into multiple segments, with each segment connected to a specific sub-array of SRAM cells. This segmentation reduces the total length of each bit-line segment, thereby reducing the RC delay for each segment while maintaining high integration density through efficient use of the divided structure
2Productivity
If SRAM cell size is increased to improve efficiency, then cell efficiency is improved, but bit-line metal coupling capacitance increases reducing differential speed
Solution Approach 1:
The memory array is divided into multiple sub-arrays, with each sub-array connected to a specific segment of the bit-line. This segmentation reduces the number of SRAM cells connected to each bit-line segment, thereby reducing the metal coupling capacitance and improving differential speed while maintaining high cell efficiency through optimized cell design
Solution Approach 2:
Different regions of the memory array are organized into sub-arrays with locally optimized bit-line connections. Each sub-array is strategically positioned and connected to minimize coupling capacitance effects, creating local quality variations that optimize both cell efficiency and differential speed in different regions
3Productivity
If SRAM cell size is increased to improve efficiency, then cell efficiency is improved, but word-line length increases causing higher resistance and RC delay
Solution Approach 1:
The memory array is segmented into multiple sub-arrays arranged in a grid pattern, with word-lines divided into multiple shorter segments. Each word-line segment connects to a specific sub-array, reducing the total length of each word-line while maintaining efficient cell organization and access
4Adaptability or versatility
If bit-line is connected to more rows of SRAM cells, then cell coverage is improved, but bit-line metal coupling capacitance increases reducing differential speed
Solution Approach 1:
The bit-line is divided into multiple independent segments, with each segment connected to a specific subset of SRAM cell rows. This segmentation allows each bit-line segment to serve fewer rows, reducing the metal coupling capacitance and improving differential speed while collectively covering the entire memory array through the segmented structure
Data Source
AI summary
An integrated circuit structure includes an SRAM array including a first sub-array having a first plurality of rows and a plurality of columns of SRAM cells, and a second sub-array having a second plurality of rows and the plurality of columns of SRAM cells. A first bit-line and a first complementary bit-line are connected to the first and the second pass-gate MOS devices of SRAM cells in a column in the first sub-array. A second bit-line and a second complementary bit-line are connected to the first and the second pass-gate MOS devices of SRAM cells in the column in the second sub-array. The first bit-line and the first complementary bit-line are disconnected from the second bit-line and the second complementary bit-line. A sense amplifier circuit is electrically coupled to, and configured to sense, the first bit-line, the first complementary bit-line, the second bit-line, and the second complementary bit-line.