SRAM Subarray Voltage Control for Leakage Reduction
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Solution Overview
Problem
Shrinking semiconductor integrated circuit feature sizes lead to undesirable current leakage in SRAM cells during both active and standby modes of operation, as the balance between high packing density and yield is challenging to maintain, particularly due to subthreshold leakage paths in memory cells.
Innovation Solution
A method is introduced to determine the minimum operating voltage for each subarray in a memory array, applying a first voltage to subarrays with a minimum operating voltage greater than a predetermined voltage and a second voltage to those with a minimum operating voltage less than the predetermined voltage, using voltage drop elements (VDEs) and fuses to selectively adjust the supply voltage, thereby reducing power consumption without compromising operating efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If feature sizes are shrunk to increase packing density, then memory density is improved, but current leakage increases
Solution Approach 1:
The patent applies different voltage levels to different subarrays based on their individual minimum operating voltage characteristics. Subarrays are categorized into groups (e.g., first group receives first voltage, second group receives second voltage) according to their specific Vmin values, allowing each subarray to operate at its optimal voltage level rather than forcing uniform voltage across all subarrays.
Solution Approach 2:
The patent changes the operating voltage parameter selectively for different subarrays. By determining the minimum operating voltage for each subarray and applying appropriate voltage levels (e.g., higher voltage for subarrays with higher Vmin, lower voltage for subarrays with lower Vmin), the system optimizes power consumption while maintaining operational correctness.
2Ease of manufacture
If uniform voltage is applied to all subarrays, then manufacturing simplicity is maintained, but power consumption increases
Solution Approach 1:
The patent segments the memory array into multiple subarrays and further divides them into groups based on their minimum operating voltage characteristics. This segmentation allows different voltage levels to be applied to different groups, optimizing power consumption. The segmentation is implemented through voltage drop elements connected to specific subarray groups, enabling granular voltage control without requiring complete redesign of the memory architecture.
Solution Approach 2:
The patent introduces dynamic voltage adjustment capability where the operating voltage for different subarray groups can be changed based on operational requirements. Voltage drop elements can be selectively activated or deactivated to change the voltage level applied to specific subarray groups, providing dynamic power management flexibility.
3Reliability
If higher voltage is applied to ensure operating reliability, then access time specifications are met, but power consumption increases
Solution Approach 1:
The patent ensures that each subarray receives the minimum voltage necessary to meet its access time specifications by determining individual Vmin values and categorizing subarrays into voltage groups. This localized voltage optimization ensures reliability for each subarray without applying unnecessarily high voltage to all subarrays, thereby reducing overall power consumption.
Data Source
AI summary
A method of programming a memory array having plural subarrays is disclosed. (FIG. 3). The method includes determining a minimum operating voltage (Vmin) for each subarray of the plural subarrays (306). A first voltage is applied to each subarray having a minimum operating voltage greater than a predetermined voltage (420, 422, 424). A second voltage is applied to each subarray having a minimum operating voltage less than the predetermined voltage (308 and 426, 428).