SRAM Supplementary Driver Circuit for Write Efficiency
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Solution Overview
Problem
As semiconductor integrated circuits (ICs) become smaller and more complex, decreasing operating voltages affect IC performance, particularly in static random access memory (SRAM) devices, where existing technologies struggle to efficiently manage voltage levels during write operations, leading to inefficiencies in data storage and retrieval.
Innovation Solution
The implementation of a supplemental driver circuit configured to pull the voltage level of data lines to a specific voltage level during write operations in SRAM, utilizing a combination of primary and secondary driver circuits and signal sensors to overcome bit line and bit line bar resistances, thereby enhancing data storage efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Volume of moving object
If operating voltages are decreased to enable smaller and more complex ICs, then IC size and complexity are improved, but write operation efficiency and data storage performance deteriorate
Solution Approach 1:
The driver circuit is segmented into a primary driver circuit and a supplementary driver circuit. The primary driver circuit handles normal write operations, while the supplementary driver circuit is selectively activated to provide additional driving current when needed, such as during difficult write operations or when lower voltage levels are applied. This segmentation allows the system to maintain compact size while preserving write efficiency through coordinated operation of the two driver circuits.
2Volume of moving object
If operating voltages are decreased to enable smaller ICs, then IC size is improved, but voltage level management during write operations deteriorates
Solution Approach 1:
The supplementary driver circuit acts as an intermediary that bridges the gap between the reduced operating voltage and the required voltage levels for reliable write operations. It provides additional voltage boosting capability and current driving strength when the primary driver circuit cannot sufficiently overcome bit line resistance at lower voltages, thereby maintaining reliable voltage level management throughout the write operation.
3Productivity
If bit line resistance is reduced to improve write efficiency, then write operation efficiency is improved, but device complexity increases
Solution Approach 1:
The supplementary driver circuit is dynamically controlled through a control signal that selectively activates it based on the specific write operation requirements. The control logic determines when supplementary driving is needed, allowing the system to adapt its complexity level to the operational demands, thereby improving write efficiency only when necessary without permanently increasing device complexity.
Data Source
AI summary
A static random access memory includes a first and second memory cell array, a first word line, a bit line, a bit line bar, a primary driver circuit, and a first and second supplementary driver circuit. The first supplementary driver circuit is configured to pull a voltage of a first signal of the bit line or a second signal of the bit line bar to a first voltage level during a write operation in response to a supplementary driver circuit enable signal. The second supplementary driver circuit is configured to sense the voltage of the first or second signal. The second supplementary driver circuit includes a first pass-gate transistor. A first terminal of the first pass-gate transistor is coupled to a reference voltage supply. A second terminal of the first pass-gate transistor is electrically floating. A third terminal of the first pass-gate transistor is coupled to a first node.