SRAM Bit Cell TDDB Testing via Isolated Transistor Biasing
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Solution Overview
Problem
Current SRAM bit cell designs lack a method for individual Time Dependent Dielectric Breakdown (TDDB) stress testing due to cross-coupling of bit cell devices, which prevents accurate evaluation of reliability and prediction of End of Life aging.
Innovation Solution
A modified 6T SRAM design (SRAM_6T_RE) with a gate-to-gate metal connection and floating diffusion contacts allows for individual TDDB stress testing by isolating transistors and applying specific biasing conditions, enabling independent stress testing of pull-up, pull-down, and pass gate devices.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a conventional SRAM bit cell design is used, then the device structure is simple and manufacturing is easy, but individual TDDB stress testing cannot be performed due to cross-coupling of bit cell devices
Solution Approach 1:
The patent segments the SRAM bit cell into isolated transistor components (pull-up, pull-down, pass gate) that can be individually stressed for TDDB testing. By dividing the cross-coupled bit cell structure into separable testing units with independent biasing, each transistor can be tested independently while maintaining overall device functionality.
Solution Approach 2:
The patent extracts the testing capability from the conventional cross-coupled bit cell structure by removing the interdependencies that prevent individual transistor stress. This is achieved through modified connections that allow isolation of specific transistors for TDDB testing while maintaining the essential SRAM functionality.
2Measurement precision
If cross-coupled bit cell devices are used, then the SRAM functionality is maintained, but accurate evaluation of individual transistor reliability is prevented
Solution Approach 1:
The patent introduces dynamic biasing capabilities that allow the SRAM bit cell to switch between operational mode (cross-coupled) and testing mode (individually biased). This dynamic reconfiguration enables precise measurement of individual transistor characteristics while maintaining ease of operation through automated biasing control.
3Reliability
If individual TDDB stress testing is enabled, then wear-out prediction accuracy is improved, but the device structure becomes more complex
Solution Approach 1:
The modified SRAM bit cell structure serves multiple functions: it maintains standard SRAM operational functionality while simultaneously enabling individual TDDB stress testing of each transistor. The universal design allows the same structure to be used for both normal operation and reliability characterization, improving wear-out prediction without requiring separate test structures.
Data Source
AI summary
A semiconductor device configured for individual reliability testing of a bit cell in a static random-access memory (SRAM). An SRAM includes a plurality of transistors. A first inverter and a second inverter cross-coupled to the first inverter are constructed of the plurality of transistors. A first access transistor and a second access transistor of the plurality of transistors are configured to share a word line bias. The second inverter and the second access transistor have a shared first gate connection and form respective bit cell devices each with two contacts. At least one contact of each of the respective bit cell devices is a floating diffusion contact, and a second contact of each of the respective bit cells is configured to be individually biased for reliability testing.