SRAM Testability Circuit with Read-Write Path Decoupling
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Solution Overview
Problem
The existing SRAM designs face challenges in fault diagnosis due to the lack of effective testability in the external control circuit area, making it difficult to locate and diagnose faults, which increases the complexity and time required for fault determination.
Innovation Solution
The proposed design includes a fault diagnosis logic control module and a read/write path decoupling circuit that allows for separate detection modes of the write and read paths, enabling the SRAM to function as a dual-port memory cell, improving storage density and fault diagnosis efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Difficulty of detecting and measuring
If the external control circuit area uses a regular layout like the memory cell area, then fault location becomes easier, but the circuit functionality and density are compromised
Solution Approach 1:
The external control circuit area is segmented into multiple functional blocks (read path circuit, write path circuit, sense amplifier, etc.), and each block is assigned a unique identification code. This segmentation allows faults to be localized to specific blocks while maintaining the irregular layout required for proper circuit functionality.
Solution Approach 2:
An intermediary identification code system is introduced between the physical circuit layout and the fault diagnosis process. The identification codes act as mediators that map irregular physical locations to diagnosable logical units, enabling fault location without requiring a regular physical layout.
2Quantity of substance
If the read and write paths are integrated in a single-port structure, then storage density is improved, but fault diagnosis complexity increases
Solution Approach 1:
The integrated read and write paths are segmented into distinct functional blocks, each with unique identification codes. The read path, write path, sense amplifier, and other components are separately identified, allowing faults to be diagnosed without the complexity of analyzing the entire integrated system.
Solution Approach 2:
Different local regions of the circuit are given different identification characteristics. Each functional block (read path, write path, sense amplifier) has its own identification code, enabling localized fault diagnosis while maintaining the overall integrated single-port structure for high storage density.
3Difficulty of detecting and measuring
If separate read and write paths are used with dual-port structure, then fault diagnosis becomes easier, but storage density decreases
Solution Approach 1:
The single-port memory cell structure is given multi-functionality to perform both read and write operations. By adding the identification code system and control logic, the same physical path can be universally used for both reading and writing, achieving fault diagnosis capability without requiring separate dual-port structures.
Solution Approach 2:
The read path and write path functionalities are merged into a single integrated path structure. The identification code system merges the diagnostic capabilities of separate paths with the space efficiency of a single path, allowing fault diagnosis while maintaining high storage density through the combined structure.
4Reliability
If comprehensive test circuits are added to the external control circuit area, then fault diagnosis capability is improved, but circuit complexity and area increase
Solution Approach 1:
The complex test circuit functionality is extracted from the main operational circuits and implemented through a separate identification code system. Rather than adding comprehensive test circuits to the read/write paths, the patent extracts the diagnostic function into a lightweight coding and comparison system that works with the existing circuit structure.
Solution Approach 2:
Instead of adding physical test circuits that copy the functionality of the main circuits, the patent uses a logical copy approach through identification codes. The codes represent the structural information of the circuit blocks, enabling diagnosis through code comparison rather than through physical test circuit copies.
Data Source
AI summary
The present application discloses a design for testability circuit of an SRAM. In a write path circuit detection mode of a fault diagnosis logic control module, a write path circuit is in an on state, a write data bit multiplexer is in a selected state, a read data bit multiplexer is in a deselected state, a read path circuit is in an on state, and a memory cell is in a selected state; in a read path circuit detection mode, the write path circuit is in an off state, the write data bit multiplexer is in a selected state, the read data bit multiplexer is in a deselected state, the read path circuit is in an on state, and the memory cell is in a deselected state. A bit line signal end is connected to a test signal outputted by a signal generation circuit.