Threshold-Tracked SRAM Virtual Ground for Standby Leakage Control
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing solutions for reducing standby leakage current in SRAM memory circuits either increase the physical size of memory cells, require complex fabrication processes, or lack effective control over virtual ground voltage, compromising data retention reliability.
Innovation Solution
A system that maintains a virtual ground node in SRAM arrays by generating a threshold reference voltage based on the threshold voltage of memory cell transistors, using a multiplier circuit to produce a virtual ground reference voltage equal to the difference between the positive supply voltage and a product of the threshold voltage, and a leakage reduction circuit to regulate the virtual ground node, ensuring data retention while minimizing leakage current.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of energy
If transistor stacks or self-reverse bias techniques are used to reduce leakage current, then leakage current is reduced, but the memory cell area increases significantly
Solution Approach 1:
The patent changes the voltage parameter at the virtual ground node by dynamically adjusting it based on the threshold voltage of memory cell transistors. By maintaining the virtual ground voltage at approximately 1.5 times the threshold voltage, the patent reduces leakage current without requiring additional transistors or increasing cell area, thus resolving the contradiction between leakage reduction and area conservation
2Area of moving object
If simple gated-ground or virtual ground techniques are used, then area is saved, but control over virtual ground voltage is poor
Solution Approach 1:
The patent implements a feedback mechanism where the virtual ground voltage is dynamically adjusted based on the threshold voltage of memory cell transistors. The system monitors the threshold voltage and automatically maintains the virtual ground voltage at the optimal level (1.5 times threshold voltage), providing precise voltage control without increasing cell area, thus resolving the contradiction between area savings and voltage control reliability
3Loss of energy
If dynamic threshold voltage technique or body biasing is used, then leakage current is reduced, but fabrication process complexity increases
Solution Approach 1:
The patent employs a self-service approach where the virtual ground voltage is automatically adjusted based on the inherent threshold voltage of the memory cell transistors themselves. The system uses the transistors' own electrical characteristics to regulate the virtual ground voltage, eliminating the need for separate body biasing circuits or triple well fabrication processes, thus reducing leakage current without increasing fabrication complexity
Data Source
AI summary
A method and system are provided for maintaining a virtual ground node of an SRAM memory array at a minimum level sufficient for maintaining data retention. A circuit can maintain the virtual ground node at a virtual ground reference voltage of VDD−(1.5*Vth), or maintain 1.5*Vth across the memory cells, where Vth is a threshold voltage of an SRAM memory cell transistor and VDD is a positive supply voltage. By tracking the Vth of the memory cell transistors in the SRAM array, the circuit reduces leakage current while maintaining data integrity. A threshold voltage reference circuit can include one or more memory cell transistors (in parallel), or a specially wired memory cell to track the memory cell transistor threshold voltage. The value of the virtual ground reference voltage can be based on a ratio of feedback chain elements in a multiplier circuit.