SRAM Timing Control Engine for Power and Speed Optimization
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Solution Overview
Problem
Conventional SRAM devices face issues with unnecessary power consumption and failure to utilize fast global clock signals due to reliance on tracking circuits that account for worst-case conditions, leading to slower operation times.
Innovation Solution
A timing control engine is introduced to compare global clock signals with simulated enable signals, allowing for the selection of the faster falling edge to determine the operation time window, thereby optimizing power usage and enabling faster clock signal utilization.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If tracking circuits are used to account for worst-case conditions, then reliability is improved, but operation speed deteriorates and power consumption increases
Solution Approach 1:
The patent segments the timing control into two independent parts: a fast global clock signal path and a slow tracking circuit path. The global clock signal provides the ideal timing window, while the tracking circuit only needs to detect whether the operation completed, not to control the timing window itself. This segmentation allows the system to use the fast global clock for timing while the tracking circuit operates at its slower speed for verification.
Solution Approach 2:
The patent introduces an intermediary mechanism that compares the global clock signal with the tracking circuit output. The global clock signal acts as a reference that determines the actual operation time window, while the tracking circuit provides verification. This intermediary comparison allows the system to bypass the slow tracking circuit timing and use the fast global clock timing instead.
2Reliability
If tracking circuits account for worst-case conditions, then reliability is improved, but power consumption increases
Solution Approach 1:
The patent segments the power consumption sources by separating the global clock signal distribution (which consumes power continuously but at low levels) from the tracking circuit operation (which consumes power during verification). This allows the system to minimize tracking circuit activation and reduce overall power consumption while maintaining reliability through the global clock's precise timing control.
Solution Approach 2:
The global clock signal serves the dual purpose of both clocking the overall system and providing the reference timing for operation windows. This self-service capability eliminates the need for the tracking circuit to generate timing signals, reducing its activity and associated power consumption while maintaining system reliability.
3Speed
If global clock signals are used directly, then operation speed is improved, but timing accuracy deteriorates due to not accounting for signal path variations
Solution Approach 1:
The patent introduces the tracking circuit as an intermediary that specifically measures and accounts for signal path variations. The tracking circuit monitors the actual signal propagation through the memory array and provides correction information. This intermediary role allows the fast global clock to provide the base timing while the tracking circuit ensures accuracy by compensating for path variations.
Solution Approach 2:
The patent dynamically adjusts the interpretation of timing parameters by comparing the global clock signal characteristics with the tracking circuit output. When signal path variations are detected, the system modifies the effective timing window parameters based on the tracking circuit feedback, thereby maintaining timing accuracy despite using the fast global clock signal.
Data Source
AI summary
A memory device includes a memory array that comprises at least a bit cell configured to store a data bit; a tracking circuit, coupled to the memory array, and configured to provide an enable signal in response to a first timing edge of a clock signal, wherein the enable signal emulates an electrical signal path propagating the memory array; and a control logic circuit comprising a timing control engine coupled to the tracking circuit, wherein the timing control engine is configured to select a faster timing edge between a second timing edge of the clock signal and a third timing edge of the enable signal so as to terminate an ongoing operation of the bit cell.