SRAM Timing Control With Tracking Bit Line for Low-VDD Writes
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Solution Overview
Problem
Static random access memories (SRAM) face challenges in reducing leakage current while maintaining the probability of successful write operations, particularly when the power supply voltage (VDD) is set near the minimum required level (Vccmin), which can lead to increased write failures due to insufficient voltage difference for overriding stored data.
Innovation Solution
The implementation of a write assist circuit that temporarily pulls the bit line voltage to a transient negative voltage level during write operations, assisted by a timing control circuit that generates a negative bit line trigger signal with adaptive timing to ensure correct voltage levels are achieved, thereby enhancing the chances of successful data writing even at lower VDD levels.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of energy
If VDD is set near Vccmin to reduce leakage current, then power consumption is reduced, but write operation reliability deteriorates due to insufficient voltage difference
Solution Approach 1:
The write assist circuit performs preliminary action by pre-charging the bit line to a negative voltage level before the actual write operation. This preliminary voltage preparation creates a larger voltage differential that enables successful write operations even when the main power supply VDD is reduced near Vccmin, thus maintaining write reliability while allowing lower operating voltage
Solution Approach 2:
The invention changes the voltage parameter of the bit line from conventional levels to a transient negative voltage level during write operations. This parameter change in the bit line voltage creates sufficient voltage difference to override stored data in the SRAM cell, enabling reliable writes at reduced VDD levels while maintaining low leakage current
2Reliability
If VDD is increased to improve write operation probability, then write reliability improves, but leakage current increases
Solution Approach 1:
The write assist circuit performs preliminary charging of the bit line to a negative voltage level before the write operation. This preliminary action creates a larger voltage differential that enables successful writes at lower VDD levels, thus achieving good write reliability without increasing the main power supply voltage and avoiding increased leakage current
Solution Approach 2:
The invention changes the bit line voltage parameter to a transient negative level during writes, which provides sufficient voltage difference for reliable write operations at reduced VDD. This allows maintaining write reliability while operating at lower VDD that reduces leakage current
Data Source
AI summary
A circuit comprises a memory array, a tracking bit line and a timing control circuit. The memory array comprises a plurality of tracking cells. The tracking bit line is coupled between a first node and the plurality of tracking cells. The timing control circuit is coupled to the first node and comprises a Schmitt trigger. The Schmitt trigger generates a negative bit line enable signal in response to that a voltage level on the first node being below a low threshold voltage value of the Schmitt trigger. The timing control circuit generates a negative bit line trigger signal according to the negative bit line enable signal for adjusting voltage levels of a plurality of bit lines of the memory array.