SRAM Timing Control Circuit for Negative Bit Line Write Assist

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Solution Overview

Problem

Static random access memories (SRAM) face challenges in reducing leakage current while maintaining the ability to perform successful write operations, particularly when the power supply voltage (VDD) is set close to the minimum required voltage (Vccmin), which increases the likelihood of write failures due to insufficient voltage difference between VDD and VSS.

Innovation Solution

The implementation of a write assist circuit that temporarily pulls the bit line voltage to a transient negative voltage level (NVSS) during write operations, triggered by a timing control circuit to ensure data can be written into SRAM bit cells successfully, even when VDD is set at a lower level to reduce leakage current.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Loss of energy

If the power supply voltage VDD is set close to Vccmin to reduce leakage current, then power consumption is reduced, but the probability of successful write operations decreases

Engineering Contradiction:

Improveleakage currentVSAvoidwrite operation success probability

Core Design Contradiction:

Loss of energyVSReliability

Solution Approach 1:

The write assist circuit performs preliminary action by pre-charging the bit line to a voltage higher than VDD before the write operation. This preliminary voltage preparation ensures that even when VDD is close to Vccmin, there is sufficient voltage difference to drive the write operation successfully, thus resolving the contradiction between low power consumption and write reliability

Inventive Principle:

Principle #10Preliminary action

Solution Approach 2:

The write assist circuit acts as an intermediary between the memory cell and the write driver. It introduces an intermediate voltage level (higher than VDD) to the bit line, which mediates the voltage difference requirement for successful write operations while allowing the main power supply VDD to remain at low levels for reduced leakage current

Inventive Principle:

Principle #24Intermediary (Mediator)

2Loss of energy

If the power supply voltage VDD is set close to Vccmin to reduce leakage current, then power consumption is reduced, but the voltage difference between VDD and VSS becomes insufficient for successful writes

Engineering Contradiction:

Improveleakage currentVSAvoidvoltage difference

Core Design Contradiction:

Loss of energyVSForce

Solution Approach 1:

Inventive Principle:

Principle #10Preliminary action

Solution Approach 2:

The write assist circuit changes the voltage parameter of the bit line dynamically. During the write operation, it temporarily raises the bit line voltage above VDD to provide sufficient voltage difference, then returns it to normal levels. This parameter change allows sufficient write voltage difference while maintaining low VDD for reduced leakage current

Inventive Principle:

Principle #35Parameter changes

Data Source

PatentUS12198754B2Timing control circuit of memory device with tracking word line and tracking bit line

Publication Date: 2025.01.14 TAIWAN SEMICONDUCTOR MANUFACTURING CO LTD

AI summary

A circuit comprises a memory array, a tracking bit line and a timing control circuit. The memory array comprises a plurality of tracking cells. The tracking bit line is coupled between a first node and the plurality of tracking cells. The timing control circuit is coupled to the first node and comprises a Schmitt trigger. The Schmitt trigger generates a negative bit line enable signal in response to that a voltage level on the first node being below a low threshold voltage value of the Schmitt trigger. The timing control circuit generates a negative bit line trigger signal according to the negative bit line enable signal for adjusting voltage levels of a plurality of bit lines of the memory array.