SRAM Timing Tracking via Internal Pulse Routing
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Solution Overview
Problem
The variability in access time to SRAM bit cells due to their relative position within the array and operational characteristics of SRAM components makes reliable timing estimation challenging, affecting system consistency and performance.
Innovation Solution
A memory apparatus and method that includes a pulse generator, conductor, and timing measurement circuit to generate a test signal for a test bit cell, allowing for concurrent activation of word and bit lines to determine time delays, utilizing existing SRAM components without altering front-end-of-line or M0 components, enabling accurate timing tracking within the SRAM array.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If external timing tracking circuits are used to monitor SRAM timing variations, then measurement precision is improved, but device complexity increases
Solution Approach 1:
The SRAM array performs timing measurement functions using its own internal resources. Test bit cells and enlisted bit lines within the SRAM array are used to track propagation times and measure timing variations, eliminating the need for separate external timing tracking circuits. The SRAM array serves both its memory function and timing measurement function.
Solution Approach 2:
Existing SRAM components including bit lines, word lines, and test bit cells are repurposed to serve dual functions: normal memory operations and timing tracking. The enlisted bit lines that are disabled from addressing SRAM cells are instead used to conduct timing tracking signals, demonstrating multi-functionality of existing infrastructure.
2Adaptability or versatility
If test bit cells and enlisted bit lines are used for timing tracking, then timing measurement capability is added, but SRAM array functionality is reduced
Solution Approach 1:
The SRAM array is segmented into nominal bit cells for normal memory operations and test bit cells for timing tracking. The bit lines are also segmented into those addressing nominal cells and those enlisted for timing tracking. This segmentation allows independent operation of timing measurement without affecting normal memory throughput.
Solution Approach 2:
Specific bit lines are extracted from the normal memory addressing function and assigned to timing tracking purposes. These enlisted bit lines are disabled from addressing SRAM cells, separating the timing measurement function from the memory access function to avoid interference.
Data Source
AI summary
A timing tracking circuit is configured within a functional memory array, obviating the need for a separate, standalone timing tracking circuit. A generated pulse is routed circuitously through conductors enlisted for timing purposes, to trigger switching of a test cell in the array, which discharges an associated bit line from a pre-charged high value. The pulled down signal resulting from the discharge is detected at a measurement unit to infer timing characteristics of the memory array. The timing tracking circuitry is implemented by re-purposing certain conductors, test cells and dummy cells inserting certain conductive or nonconductive regions at one or more layers or at vias between layers to alter operation of the respective conductors and cells. Cells and conductors not enlisted for timing remain available for efficient, reliable memory access performance.