SRAM with Tunnel Magnetoresistance Structures for Non-Volatile Data Retention
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Solution Overview
Problem
Conventional SRAM devices lose stored data instantly when power is shut off due to their volatile nature, necessitating a solution to enhance non-volatile data storage capabilities without altering the existing architecture.
Innovation Solution
Integration of tunnel magnetoresistance (TMR) structures into the SRAM circuit, specifically coupling TMR structures with inverters and pass transistors, allowing for an additional magnetoresistive random access memory (MRAM) mode that enables data retention even when power is cut off by altering resistance states.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If conventional SRAM architecture is used, then high access speed is achieved, but data is lost instantly when power is shut off
Solution Approach 1:
The patent merges SRAM and MRAM architectures into a unified 6T-SRAM cell where TMR structures are integrated with the SRAM circuit. The TMR structure is coupled to the first inverter and the first pull-down transistor, creating a hybrid cell that combines the high-speed access of SRAM with the non-volatile data retention of MRAM in a single integrated structure
Solution Approach 2:
The patent creates a multi-functional memory cell that can operate in both SRAM mode (for high-speed volatile storage) and MRAM mode (for non-volatile storage). The circuit can selectively access either the SRAM storage nodes or the TMR structure depending on the operation mode, providing universal functionality for both volatile and non-volatile memory operations within the same architecture
2Reliability
If TMR structures are integrated into SRAM, then non-volatile data storage is achieved, but device complexity increases
Solution Approach 1:
The patent merges SRAM and MRAM functionalities into a single 6T-SRAM cell structure, eliminating the need for separate SRAM and MRAM cells. The TMR structure is seamlessly integrated with the existing SRAM transistors and inverters, combining multiple memory functions in one unified device to reduce overall system complexity despite the advanced functionality
Solution Approach 2:
The patent designs a universal memory cell that performs both volatile SRAM operations and non-volatile MRAM operations through a single integrated circuit. This multi-functional approach eliminates the need for separate dedicated circuits for different memory types, reducing overall device complexity while providing diverse memory capabilities
3Reliability
If TMR structures are coupled with inverters and pass transistors, then data retention during power shutdown is enabled, but manufacturing precision requirements increase
Solution Approach 1:
The patent integrates the TMR structure directly into the standard SRAM fabrication process, merging the magnetoresistive element with the transistor and inverter structures. This integration allows all components to be manufactured together in a unified process flow, reducing the need for separate precision alignment steps and lowering overall manufacturing precision requirements compared to hybrid approaches
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The integration of TMR structures into SRAM devices provides a non-volatile data storage capability, allowing signals to be retained during power shutdown and efficiently read and written, effectively addressing the volatility issue of conventional SRAMs.
Implementation Method 1
a first tunnel magnetoresistance (TMR) structure coupled to the first inverter and the first pull-down transistor, and a second TMR structure coupled to the second inverter and the second pull-down transistor
Data Source
AI summary
A static random access memory (SRAM) structure includes a first inverter comprising a first pull-up transistor and a first pull-down transistor, a second inverter comprising a second pull-up transistor and a second pull-down transistor, a first pass transistor coupled to the first inverter, and a second pass transistor coupled to the second inverter. Preferably, the first inverter is coupled to a first tunnel magnetoresistance (TMR) structure and the second inverter is coupled to a second TMR structure.