SRAM Tracking Circuit Optimizes Power and Write Margins
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Solution Overview
Problem
The integration of static random access memory (SRAM) devices is challenging due to their smaller capacity per area compared to dynamic random access memory (DRAM), and they require complex peripheral circuits, high power consumption, and frequent refresh operations.
Innovation Solution
The SRAM device includes a memory cell array with row and column tracking circuits that generate control pulses based on internal clocks, resistances, and capacitances of word and bit lines, optimizing write and read operations by adjusting power supply voltages and pulse widths.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If SRAM devices are integrated to increase capacity, then storage capacity per area is improved, but device complexity and manufacturing difficulty increase
Solution Approach 1:
The memory array is divided into multiple banks, with each bank containing multiple bit cells arranged in rows and columns. This segmentation allows the large memory structure to be managed as smaller, independent units, reducing the complexity of integration while achieving high total capacity.
Solution Approach 2:
The patent organizes memory cells in a two-dimensional grid structure (rows and columns) rather than linear arrangement. This dimensional organization efficiently packs more cells per area while simplifying the addressing and control logic through row-column decoding schemes.
2Adaptability or versatility
If control pulses are applied to change voltage levels for write and read operations, then operational flexibility is improved, but power consumption increases
Solution Approach 1:
The memory device uses periodic clock signals to control the timing of write and read operations. By synchronizing voltage level changes and data transfers to specific clock cycles, the device achieves operational flexibility while minimizing power consumption by keeping circuits in low-power states between active periods.
Solution Approach 2:
The patent employs dynamic voltage scaling where the voltage levels applied to word lines and bit lines are adjusted based on the specific operation being performed (read vs. write). This dynamic adjustment allows the device to adapt to different operational requirements while consuming only the necessary power for each operation.
3Reliability
If refresh operations are implemented to maintain data, then data integrity is improved, but operational complexity and power consumption increase
Solution Approach 1:
The SRAM bit cells are designed with self-holding latch circuits that automatically maintain their state without external refresh operations. The cross-coupled transistor structures in each bit cell create stable bistable states that persist indefinitely, eliminating the need for periodic refresh cycles and associated control complexity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances the SRAM's operational efficiency by reducing power consumption and improving write margins, while maintaining data integrity without the need for refresh operations.
Implementation Method 1
a driver connected with a first wire including a first capacitor corresponding to a length of one of the plurality of word lines and a first resistor corresponding to the length of the one of the plurality of word lines, the driver configured to output a first signal based on a value of the first resistor and a capacitance of the first capacitor
Implementation Method 2
a first inverter that includes a first end connected with a second wire including a second resistor corresponding to a length of one of the plurality of bit lines and a second end connected with a third wire including a second capacitor corresponding to the length of the one of the plurality of bit lines, the first inverter configured to output a second signal based on a value of the second resistor, a capacitance of the second capacitor, and the first signal
Data Source
AI summary
Disclosed is a static random access memory (SRAM) device. According to example embodiments of the present disclosure, a control logic of the SRAM device may include a tracking circuit connected with metal lines for tracking the number of columns of a memory cell array and the number of rows of the memory cell array. By the tracking circuit, a length of word lines of the memory cell array and a length of bit lines of the memory cell array may be tracked. The control logic of the SRAM device may generate control pulses optimized for the size of the memory cell array, based on a tracking result(s) of the tracking circuit. Accordingly, a power and a time necessary for a write operation and a read operation may be reduced.