SRAM Tracking Circuitry for Word Line Pulse Width Control
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Solution Overview
Problem
Static random access memory (SRAM) cells consume large active power due to non-optimized pulse widths of word lines, which affects efficiency in high-speed communication, image processing, and system-on-chip (SOC) applications.
Innovation Solution
The implementation of a memory device with a tracking circuit and control circuit that modulate the word line signal by using tracking cells to adjust pulse widths based on the distance from the I/O circuit or control circuit, optimizing power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If word line pulse width is increased to ensure proper memory cell operation, then reliability is improved, but active power consumption increases
Solution Approach 1:
The patent implements dynamic word line pulse width modulation where the pulse width is adjusted based on the distance between the memory cell and the I/O circuit. Tracking circuits generate delayed versions of the word line signal with different pulse widths, and the appropriate pulse width is selected dynamically based on which memory cells are being accessed. This resolves the contradiction by using longer pulse widths only when necessary for distant cells while using shorter pulse widths for nearby cells, thereby maintaining reliability while reducing overall power consumption.
Solution Approach 2:
The patent changes the temporal parameter (pulse width) of the word line signal based on spatial position (distance from I/O circuit). By varying the pulse width parameter dynamically according to the specific memory cell address being accessed, the system optimizes the balance between reliable operation and power consumption. The tracking circuits create multiple versions of the word line signal with different pulse widths, and the appropriate version is selected based on the distance to the target memory cell.
2Ease of operation
If uniform word line pulse width is used for all memory cells, then ease of operation is improved, but power consumption increases due to over-driving distant cells
Solution Approach 1:
The patent segments the memory array into multiple regions based on distance from the I/O circuit, with each region having its own tracking circuit that generates appropriately timed word line signals. This segmentation allows different pulse widths to be applied to different regions, reducing power consumption for cells that don't require long pulse widths while maintaining proper operation for distant cells. The segmentation approach maintains ease of operation by automatically selecting the appropriate pulse width based on cell location.
Solution Approach 2:
The patent applies local quality by providing different word line pulse widths to different spatial locations within the memory array. Memory cells closer to the I/O circuit receive shorter pulse widths while distant cells receive longer pulse widths. This local optimization ensures that each region receives the minimum necessary pulse width for reliable operation, avoiding the power waste of uniformly over-driving all cells while maintaining ease of operation through automatic local adaptation.
3Use of energy by moving object
If tracking circuitry is added to optimize pulse widths, then power consumption is reduced, but device complexity increases
Solution Approach 1:
The patent merges the tracking circuit functionality with the existing word line driver and memory cell structure. The tracking circuits are integrated into the word line generation path, and the delayed signals are combined with the original word line signal through logical OR operations. This merging approach reduces the overhead of adding tracking functionality by reusing existing circuit elements and combining multiple functions into unified structures, thereby reducing the increase in device complexity while achieving power consumption reduction.
Solution Approach 2:
The patent creates simplified copies of the word line signal through tracking circuits that generate delayed versions of the original signal. Instead of implementing complex adaptive pulse width modulation, the system creates multiple copies of the word line signal with different timing characteristics using simple delay circuits and latch structures. These copied signals are then selectively combined to achieve the desired pulse width optimization, reducing device complexity by using simple signal copying rather than complex modulation circuits.
Data Source
AI summary
A memory device including a first memory cell, a first tracking cell, a tracking bit line, a second tracking cell and a word line driver. The first memory cell is configured to receive a first word line signal. The first tracking cell is configured to emulate the first memory cell. The tracking bit line is configured to transmit a tracking bit line signal to the first tracking cell. The second tracking cell is configured to adjust the tracking bit line signal according to the first word line signal. The word line driver is configured to adjust the first word line signal according to the tracking bit line signal and a first distance between the second tracking cell and a common node on the tracking bit line.