SRAM Tracking Wordline Voltage Suppressor Circuit
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Solution Overview
Problem
SRAM memory designs face performance degradation due to backend interconnect resistance and capacitance, requiring complex timing loops or extra logic delays to address weak bits, which incur area penalties and poor tracking ratios.
Innovation Solution
A self-timed memory system with a tracking scheme that uses a feedback loop to emulate wordline pulse duration, employing a tracking wordline voltage suppressor and voltage divider to extend wordline pulse width based on weak bit detection, reducing area penalties and improving tracking ratios.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If multiple selectable timing loops are provided to address weak bits, then read margin is improved, but device complexity and area increase significantly
Solution Approach 1:
The patent changes the voltage level parameter of the wordline signal to extend its pulse width. By providing a reduced voltage level wordline signal (e.g., 0.7V instead of 1.0V), the pulse width is extended to accommodate weak bit cells without requiring complex timing loops or state machine control circuitry, thus improving read margin while avoiding increased device complexity
Solution Approach 2:
The patent dynamically adjusts the wordline pulse width by selectively enabling reduced voltage level signaling based on detection of weak bit cells. The system transitions from a fixed voltage level approach to a dynamic approach where the voltage level and pulse width are adjusted in real-time based on the presence of weak bits, resolving the contradiction between reliability and complexity
2Duration of action of moving object
If extra selectable logic delays with long inverter chains are provided, then timing for weak bits is improved, but area and device complexity increase
Solution Approach 1:
Instead of adding physical delay elements like long inverter chains, the patent changes the voltage parameter of the wordline signal. By reducing the voltage level, the transistor switching characteristics change, naturally extending the pulse width without requiring additional logic delay circuits, thus achieving the desired timing duration without area penalties
Solution Approach 2:
The patent creates a simplified copy of the wordline signaling mechanism that operates at reduced voltage levels. Rather than adding complex delay circuits, it implements a parallel signaling path with modified voltage characteristics that naturally provides the required pulse width extension, avoiding the area overhead of traditional delay chains
3Reliability
If conservative design with extended timing is used to accommodate weak bits, then reliability is improved, but performance of non-weak bits deteriorates
Solution Approach 1:
The patent implements a dynamic design where the wordline pulse width and voltage level are adjusted based on the presence of weak bit cells. When weak bits are detected, the system switches to reduced voltage level signaling with extended pulse width. When no weak bits are present, the system operates with normal voltage and timing, thus maintaining high performance for non-weak bits while ensuring reliability for weak bits
Solution Approach 2:
The patent uses parameter changes in the wordline signal (voltage level and pulse width) to adapt to different operational conditions. By detecting the presence of weak bits and accordingly changing the signaling parameters, the system optimizes performance for each case, avoiding the performance degradation that would result from always using conservative extended timing
Data Source
AI summary
A memory includes a clock generator for providing a first clock signal responsive to a second clock signal and a feedback signal. A feedback loop provides the feedback signal and includes a tracking wordline, a tracking bitline, a tracking bit cell, and a tracking wordline driver for driving the tracking wordline responsive to the first clock signal. The memory includes a tracking wordline level tuner for reducing a voltage level of a tracking wordline signal on the tracking wordline responsive to a weak bit control signal.