SRAM Transistor Gate Structure Optimization for Static Noise Margin

Resolve Bottlenecks,
Find Innovative Solutions
Generate Solutions

Solution Overview

Problem

Existing static random access memories (SRAM) face challenges with small static noise margin and poor read stability due to similar structures of pull-down and pass-gate transistors, limiting the improvement of the beta ratio and thus the static noise margin.

Innovation Solution

The SRAM design includes pull-down transistors and pass-gate transistors with distinct gate structures and doping concentrations, where the pull-down transistors have a higher work function and lower doping ion concentration than pass-gate transistors, increasing the beta ratio and static noise margin by optimizing the threshold voltages and saturation currents.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Ease of manufacture

If pull-down transistors and pass-gate transistors have similar structures, then manufacturing is simplified, but the beta ratio and static noise margin are limited

Engineering Contradiction:
Improvetransistor structure uniformityVSAvoidstatic noise margin
Core Design Contradiction:
Ease of manufactureVSReliability

Solution Approach 1:

The patent applies local quality by giving different gate structures to pull-down transistors and pass-gate transistors. Specifically, pull-down transistors have a first gate structure with different dimensions and electrical characteristics than the second gate structure of pass-gate transistors. This local differentiation optimizes the beta ratio and static noise margin while maintaining overall manufacturing feasibility through standardized fabrication processes.

Inventive Principle:
Principle #3Local quality

Solution Approach 2:

The patent changes physical parameters of the gate structures, including gate length, gate width, and gate oxide thickness, to differentiate between pull-down and pass-gate transistors. These parameter adjustments allow independent optimization of threshold voltages and drive currents, thereby improving the beta ratio and static noise margin without requiring complete structural redesign.

Inventive Principle:
Principle #35Parameter changes

2Reliability

If Fin-FET structure is used, then circuit control and data storage stability are improved, but device complexity increases

Engineering Contradiction:
Improvedata storage stabilityVSAvoidgate structure complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The patent segments the gate structure into distinct first and second gate structures with different configurations. The first gate structure controls the pull-down transistor while the second gate structure controls the pass-gate transistor. This segmentation allows independent optimization of each transistor's electrical characteristics while maintaining the benefits of Fin-FET technology for improved circuit control and data stability.

Inventive Principle:
Principle #1Segmentation

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This approach enhances the static noise margin and stability of SRAM by increasing the beta ratio, improving the memory's anti-interference ability and integration level.

Implementation Method 1

a portion of the first substrate region under each first gate structure is doped with first doping ions and a portion of the second substrate region under each second gate structure is doped with second doping ions

Methodology Applied
Scientific EffectIon implantation: Ion Implantation

Data Source

PatentUS10332892B2Static random access memory and fabrication method thereof
Publication Date: 2019.06.25 SEMICON MFG INT (SHANGHAI) CORP
  • US10332892B2 patent drawing
  • US10332892B2 patent drawing
  • US10332892B2 patent drawing

AI summary

An SRAM includes a substrate containing a plurality of first substrate regions and a plurality of second substrate regions, a plurality of pull-down transistors formed in the first substrate regions with each pull-down transistor including a first gate structure, and a plurality of pass-gate transistors formed in the second substrate regions with each pass-gate transistor including a second gate structure. A portion of the first substrate region under each first gate structure is doped with first doping ions and a portion of the second substrate region under each second gate structure is doped with second doping ions. Moreover, the concentration of the first doping ions is less than the concentration of the second doping ions, and the work function of the first work function layer in the first gate structures is greater than the work function of the second work function layer in the second gate structures.