SRAM Word Line Underdrive Control for Multi-Row In-Memory Compute
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Solution Overview
Problem
Existing in-memory computation circuits using standard SRAM cells face data flip issues during simultaneous access of multiple rows, leading to accuracy loss and performance degradation, which conventional solutions like fixed word line underdrive or specialized bitcell designs fail to adequately address without increasing circuit area or reducing read current variability.
Innovation Solution
Implementing an adaptive word line underdrive control system that adjusts the supply voltage based on integrated circuit process and temperature conditions, using a voltage generator circuit to modulate the word line driver supply voltage and incorporate bleeder transistors or replica circuits to optimize word line underdrive levels.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If fixed word line underdrive is applied to all process corners, then data flip rate is reduced, but read current variability increases and computation accuracy is lost
Solution Approach 1:
The patent implements dynamic word line underdrive adjustment by sensing the actual process corner characteristics and temperature conditions, then adaptively setting the word line underdrive voltage level. This dynamic approach allows the system to optimize between data flip prevention and read current stability based on real-time operating conditions, rather than using a fixed underdrive level for all scenarios
Solution Approach 2:
The system changes the word line underdrive voltage parameter based on detected process and temperature conditions. By adjusting this critical voltage parameter adaptively, the system maintains optimal read margins across different operating conditions while preventing excessive data flips, thereby resolving the contradiction between reliability and measurement precision
2Reliability
If word line underdrive is increased to prevent data flips, then reliability improves, but read current decreases and performance degrades
Solution Approach 1:
The system dynamically adjusts the word line underdrive voltage based on sensed process corners and temperature, applying stronger underdrive only when necessary to prevent data flips. This dynamic control maintains higher read current when conditions permit, thus preserving performance while ensuring reliability when needed
Solution Approach 2:
The word line underdrive voltage parameter is adjusted based on operating conditions. By changing this parameter adaptively rather than using a fixed high value, the system prevents data flips when required while maintaining optimal read current levels during normal operation, thus resolving the reliability-productivity tradeoff
3Area of stationary object
If conventional word line driving is used during simultaneous row access, then circuit area is minimized, but data flip issues occur and computation accuracy is lost
Solution Approach 1:
The patent incorporates feedback mechanisms that sense process corner characteristics and temperature conditions, then use this information to adjust word line underdrive settings. This feedback-based adaptive control enables the system to maintain computation accuracy during simultaneous row access without requiring additional circuit area for specialized bitcell designs
Solution Approach 2:
The system uses its own operational characteristics (process corner, temperature) to automatically adjust its word line driving parameters. This self-service approach enables the circuit to adapt to varying conditions and maintain accuracy without external intervention or additional specialized hardware
Data Source
AI summary
An in-memory computation circuit includes a memory array with SRAM cells connected in rows by word lines and in columns by bit lines. Each row includes a word line drive circuit powered by an adaptive supply voltage. A row controller circuit simultaneously actuates word lines in parallel for an in-memory compute operation. A column processing circuit processes analog voltages developed on the bit lines in response to the simultaneous actuation to generate a decision output for the in-memory compute operation. A voltage generator circuit generates the adaptive supply voltage for powering the word line drive circuits during the simultaneous actuation. A level of the adaptive supply voltage is modulated dependent on integrated circuit process and/or temperature conditions in order to optimize word line underdrive performance and inhibit unwanted memory cell data flip.