SRAM Fabrication with Variable Insulating Layer Thickness
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Solution Overview
Problem
Current SRAM architecture faces challenges in producing desirable patterns as the pitch of the exposure process decreases, making it difficult to enhance exposure quality.
Innovation Solution
A method for fabricating a stack random access memory (SRAM) device involves creating a substrate with distinct regions, forming front and back gates with varying insulating layer thicknesses, and using photo-etching processes to form specific gate structures, allowing for different threshold voltages and improved read margin.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Length of moving object
If current SRAM architecture is used with decreasing exposure pitch, then device scaling is achieved, but exposure quality and pattern formation deteriorate
Solution Approach 1:
The patent introduces a third dimension by forming back gates beneath the front gates, creating a stacked configuration. This vertical dimension allows for additional control mechanisms that compensate for the limitations of planar scaling, enabling better pattern formation and exposure quality even as pitch decreases.
Solution Approach 2:
The patent implements different insulating layer thicknesses in different regions (first region vs. second region) to create locally optimized conditions. By varying the insulating layer thickness beneath different gates, the invention achieves localized control over electrical characteristics, improving overall device performance and exposure quality.
2Reliability
If insulating layer thickness is varied in different regions, then beta ratio and read margin control is improved, but device complexity increases
Solution Approach 1:
The patent divides the insulating layer into distinct segments with different thicknesses corresponding to different functional regions. The first insulating layer portion beneath the first front gate has a different thickness than the second insulating layer portion beneath the second front gate, allowing independent optimization of each region's electrical characteristics.
Solution Approach 2:
The invention changes the physical parameter of insulating layer thickness to achieve different electrical characteristics in different regions. By adjusting the thickness parameter, the patent optimizes the beta ratio and read margin without fundamentally changing the device architecture or requiring additional complex components.
Data Source
AI summary
A method for fabricating semiconductor device includes the steps of: providing a substrate having a first region and a second region and the substrate comprises a semiconductor layer on top of an insulating layer; forming a first front gate on the first region of the substrate and a second front gate on the second region of the substrate; removing part of the insulating layer under the first front gate; forming a first back gate on the insulating layer under the first front gate; and forming a second back gate under the second front gate.