SRAM Cell Vertical Gate All-Around Transistor Self-Aligned Electrode
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Solution Overview
Problem
The integration of vertical transistors into SRAM chips poses challenges in reducing power consumption and increasing data storage density, particularly in portable electronics and high-speed computation applications.
Innovation Solution
The use of vertical transistors with a vertical gate all-around (VGAA) configuration and the implementation of data storage electrodes that are self-aligned to the gate lines, allowing for reduced width and preventing short-circuits, while maintaining electrical connectivity between source and gate regions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by moving object
If conventional transistors are used in SRAM, then the transistor size and power consumption are larger, but replacing them with vertical transistors reduces size and power consumption
Solution Approach 1:
The patent transitions from planar transistors to vertical transistors by changing the dimensional orientation of the transistor structure. The vertical gate all-around (VGAA) configuration extends the gate structure into the vertical dimension, surrounding the channel region vertically, which reduces the footprint area while maintaining electrical functionality and lowering power consumption.
Solution Approach 2:
The vertical gate all-around configuration nests the gate structure around the channel region in a surrounding manner. The gate electrode wraps around the channel from multiple sides, creating a nested structure where the gate encloses the channel region, improving control over the channel while reducing overall device size.
2Quantity of substance
If vertical transistors with VGAA configuration are integrated into SRAM, then data storage density increases, but manufacturing challenges emerge
Solution Approach 1:
The patent employs preliminary alignment actions during manufacturing where the data storage electrode is pre-positioned and self-aligned to the gate line structure. This preliminary positioning ensures correct spatial relationships between components before final assembly, reducing manufacturing complexity despite the advanced vertical transistor architecture.
Solution Approach 2:
The data storage electrode is designed to be self-aligned to the gate line, where the electrode automatically positions itself relative to the gate structure during fabrication. This self-alignment mechanism eliminates the need for complex external alignment procedures, simplifying manufacturing while enabling high data storage density.
3Reliability
If data storage electrodes are self-aligned to gate lines, then short-circuits are prevented and electrical connectivity is maintained, but manufacturing precision requirements increase
Solution Approach 1:
The data storage electrode utilizes self-alignment to the gate line structure, where the electrode automatically positions itself relative to the gate during fabrication processes. This self-service positioning mechanism ensures precise alignment and prevents short-circuits between the electrode and channel region, maintaining reliable electrical connectivity while simplifying the manufacturing process.
Data Source
AI summary
A static random access memory (SRAM) cell includes first through fourth transistors being first type transistors and fifth and sixth transistors being second type transistors. Source regions of the first and second transistors are formed by a first source diffusion region, source regions of the fifth and sixth transistors are formed by second and third source diffusion regions, respectively, and source regions of the third and fourth transistors are formed by a fourth source diffusion region. The SRAM cell further includes a first data storage electrode linearly extending from a first gate line of the third and sixth transistors and electrically connecting the first gate line and the first and second source diffusion regions, and a second data storage electrode linearly extending from a second gate line of the second and fifth transistors and electrically connecting the second gate line and the third and fourth source diffusion regions.