SRAM Layout via Vertical Stacking and Segmented Metal Layers
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Solution Overview
Problem
The fabrication of existing static random access memories (SRAMs) is complex due to the high requirements of the layout-design for the metal layers, particularly the small minimum feature size and pitch of patterns, which exceed the capability of state-of-the-art fabrication processes, making the photolithography process difficult.
Innovation Solution
The method involves forming a semiconductor substrate with transistors and using a first metal layer for the word line and a second metal layer for bit lines and power source lines, altering the layout-design to increase the minimum feature size and pitch of patterns, thereby simplifying the fabrication process.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If the existing SRAM layout-design is used with small minimum feature size and pitch of patterns, then the transistor density and integration level are improved, but the photolithography process capability and fabrication complexity are worsened
Solution Approach 1:
The patent applies dimensionality change by transitioning from a planar 2D layout to a 3D stacked architecture. Multiple transistor layers are stacked vertically above each other, allowing high transistor density without reducing the minimum feature size or pitch in the lateral plane. This vertical stacking enables advanced integration while maintaining manufacturable pattern dimensions for photolithography processes.
2Reliability
If the existing metal layer layout is used, then the electrical connectivity is improved, but the fabrication process complexity is worsened
Solution Approach 1:
The patent segments the metal interconnect system into multiple distinct layers (first metal layer, second metal layer, third metal layer) with specialized functions. Each layer handles specific routing tasks, simplifying the design and fabrication of individual layers while achieving comprehensive electrical connectivity. This segmentation reduces the complexity of any single metal layer layout compared to a monolithic interconnect structure.
Data Source
AI summary
A method for fabricating a static random access memory is provided. The method includes providing a semiconductor substrate. The method also includes forming a plurality of transistors on the semiconductor substrate. Further, the method includes forming a first metal layer having a word line electrically connecting with a partial number of the transistors. Further, the method also includes forming a second metal layer having a first bit line, a second bit line, a first power source line and second power source lines electrically connect with a partial number of the transistors.