SRAM Bit Cell Architecture Using Vertical Transistor Stacking
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Solution Overview
Problem
Conventional SRAM technology faces challenges in scaling bit cell area and circuit density, with the scaling rate slowing down at the 14 nm technology node and below due to limitations in transistor design and fabrication.
Innovation Solution
The proposed solution involves a bit cell architecture with vertically stacked transistors, including pull-up, pull-down, and pass transistors, where the pull-up and pull-down transistors share a common gate electrode, and the pass transistors are arranged to form part of their respective stacks, allowing for efficient area utilization and reduced substrate area occupation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of moving object
If conventional planar transistor design is used, then manufacturing is easier, but bit cell area cannot be scaled down further at 14 nm node and below
Solution Approach 1:
The patent transitions from planar (2D) transistor layout to vertical (3D) stacked transistor architecture. Multiple transistor layers are stacked vertically above the substrate, with each layer containing pull-up, pull-down, and pass transistors. This vertical stacking enables continued bit cell area scaling at 14 nm and below by utilizing the third dimension (height) rather than further reducing lateral dimensions, thereby overcoming the physical limitations of conventional planar scaling.
2Area of moving object
If vertical stacking of transistors is implemented, then bit cell area is reduced, but device complexity increases
Solution Approach 1:
The patent merges multiple transistor functions into vertically stacked layers within a compact bit cell footprint. The first and second transistor stacks are arranged vertically, with shared source/drain regions and interconnections between layers. This merging of spatial separation with functional integration reduces the lateral area while consolidating multiple transistor operations into a unified vertical structure, managing complexity through systematic layer integration rather than scattered planar arrangements.
3Speed
If transistor dimensions are reduced, then switching speed improves, but short channel effects increase
Solution Approach 1:
The vertical stacked transistor architecture extends the effective channel control into the vertical dimension. By stacking multiple transistor layers with their channels oriented vertically rather than horizontally, the design achieves faster switching speeds through reduced effective channel lengths while the vertical gate control structure provides improved electrostatic control that mitigates short channel effects. The third-dimensional arrangement allows shorter channels without proportionally increasing leakage.
Data Source
AI summary
In an aspect of the disclosed technology, a SRAM device includes a first stack of transistors and a second stack of transistors arranged on a substrate. Each of the first and second stacks includes a pull-up transistor, a pull-down transistor and a pass transistor, where each of the transistors includes a horizontally extending channel. In each of the first and second stacks, the pull-up transistor and the pull-down transistor have a common gate electrode extending vertically therebetween, and the pass transistor has a gate electrode separated from the common gate electrode. A source/drain of each of the pull-up transistor and the pull-down transistor and a source/drain of the pass transistor included in one of the first stack and the second stack are electrically interconnected with the common gate electrode of the pull-up transistor and the pull-down transistor included in the other of the first stack and the second stack.