SRAM Cells with Vertical Gate-All-Around MOSFETs for Low Capacitance
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Solution Overview
Problem
Existing SRAM cells face challenges in achieving high read and write speeds while maintaining low parasitic capacitance in Metal-Oxide-Semiconductor Field-Effect Transistors (MOSFETs) to meet the demands of high-speed operations.
Innovation Solution
The integration of Vertical Gate-All-Around (VGAA) transistors in SRAM cells, which feature vertical channels surrounded by gate dielectrics and electrodes, reducing parasitic capacitance and allowing for reduced cell size without compromising saturation currents.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of moving object
If conventional planar MOSFETs are used in SRAM cells, then the cell size can be reduced, but the parasitic capacitance increases and speed performance deteriorates
Solution Approach 1:
The patent transitions from conventional planar (2D) MOSFETs to vertical (3D) gate-all-around MOSFETs. The gate electrode completely surrounds the channel region in three dimensions, providing superior electrostatic control and reducing parasitic capacitance while maintaining compact footprint. This dimensional change enables the channel to be controlled from all directions, improving device performance without increasing cell area.
2Ease of manufacture
If conventional planar MOSFETs are used in SRAM cells, then manufacturing processes are simpler, but read speed and write speed are insufficient for high-speed operations
Solution Approach 1:
The vertical gate-all-around structure provides enhanced electrostatic control over the channel, enabling faster switching speeds and improved carrier modulation. The 3D gate configuration reduces parasitic capacitance, which directly improves read and write speeds while maintaining compatibility with standard semiconductor manufacturing processes through sequential formation steps.
Solution Approach 2:
The patent changes the geometric parameters of the MOSFET from planar to vertical configuration. This parameter change fundamentally alters the electric field distribution and capacitance characteristics, enabling high-speed operation. The vertical channel and surrounding gate electrode create stronger field effects that accelerate carrier transport and improve switching performance.
3Object-affected harmful factors
If Vertical Gate-All-Around transistors are integrated in SRAM cells, then parasitic capacitance is reduced and saturation currents are maintained, but device structure and manufacturing process become more complex
Solution Approach 1:
The vertical gate-all-around transistor is formed through segmented processing steps: first forming the channel region and gate dielectric, then depositing the gate electrode material, and finally forming source and drain regions. This segmentation of the manufacturing process makes the complex 3D structure achievable through standard sequential fabrication techniques, reducing the practical complexity despite the advanced device architecture.
Data Source
AI summary
A Static Random Access Memory (SRAM) cell includes a first boundary and a second boundary opposite to, and parallel to, the first boundary, a first and a second pull-up transistor, a first and a second pull-down transistor forming cross-latched inverters with the first and the second pull-up transistors, and a first and a second pass-gate transistor. Each of the first and the second pull-up transistors, the first and the second pull-down transistors, and the first and the second pass-gate transistors includes a bottom plate as a first source/drain region, a channel over the bottom plate, and a top plate over the channel as a second source/drain region. The SRAM cell further includes a first, a second, a third, and a fourth active region, each extending from the first boundary to the second boundary.