Compact SRAM Cell Connection Using Expanded Via Layout
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Solution Overview
Problem
The integration of SRAM cells with microprocessors poses challenges due to the need for specialized masks and process steps, leading to increased complexity and potential for mask alignment errors, which can result in larger memory cell sizes and higher capacitance, affecting performance and data storage reliability.
Innovation Solution
A compact SRAM cell layout is developed that utilizes the same process steps and masks as microprocessor manufacturing, incorporating an expanded via structure that electrically connects transistors without additional metal wiring layers, reducing capacitance and allowing for a more compact design.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If specialized masks and process steps are used for SRAM cell manufacturing, then manufacturing precision can be maintained, but device complexity and manufacturing cost increase
Solution Approach 1:
The patent applies universality by designing the SRAM cell to use the same masks and process steps as the microprocessor manufacturing. The active areas, gates, and insulation layers are formed using identical processes, eliminating the need for specialized SRAM masks. This multi-functional approach allows the same manufacturing infrastructure to serve both microprocessor and SRAM fabrication, reducing overall device complexity while maintaining alignment precision.
Solution Approach 2:
The patent merges the SRAM cell manufacturing process with the microprocessor manufacturing process. By combining the formation of active areas, gates, and insulation layers into a single unified process sequence, the patent eliminates separate SRAM-specific process steps. This merging reduces the total number of masks and process steps while ensuring consistent manufacturing precision across both device types.
2Reliability
If additional metal wiring layers are used to connect transistors, then electrical connections can be established, but capacitance increases and cell size increases
Solution Approach 1:
The patent transitions from planar metal wiring connections to vertical via connections. Instead of using additional metal wiring layers that extend horizontally across the cell, the invention uses vias that connect transistor drains and gates through vertical paths in the insulation layers. This dimensional change from 2D wiring to 3D vertical connections reduces the horizontal space required and minimizes parasitic capacitance associated with extended metal traces.
Solution Approach 2:
The patent extracts the metal wiring layer requirement by establishing direct via connections between transistor elements. By removing the need for intermediate metal wiring layers and using vias that directly connect active areas to gates, the patent eliminates the capacitance contribution from extended metal traces while maintaining reliable electrical connections.
3Manufacturing precision
If larger memory cell size is used, then manufacturing precision requirements are reduced, but area occupied by cell increases
Solution Approach 1:
The patent reduces memory cell area by transitioning from planar metal wiring to vertical via connections. This dimensional change allows transistor elements to be positioned closer together horizontally, as the vertical vias require minimal horizontal spacing. The result is a compact cell layout that reduces area while maintaining manufacturing precision through the use of standard alignment procedures.
Solution Approach 2:
By merging the SRAM cell layout with the microprocessor circuit layout, the patent achieves compact cell dimensions that fit efficiently within the overall chip area. The unified process approach allows optimized spacing between cell elements while using the same mask alignment tolerances as the surrounding microprocessor circuitry, eliminating the need for larger cells with relaxed precision requirements.
Data Source
AI summary
An integrated circuit structure in which a gate overlies channel region in an active area of a first transistor. The first transistor includes a channel region, a source region and a drain region. A conductive contact is coupled to the drain region of the first transistor. A second transistor that includes a channel region, a source region a drain region is adjacent to the first transistor. The gate of the second transistor is spaced from the gate of the first transistor. A conductive via passes through an insulation layer to electrically connect to the gate of the second transistor. An expanded conductive via overlays both the conductive contact and the conductive via to electrically connect the drain of the first transistor to the gate of the second transistor.